GBT Project Status Paulo Moreira On behalf of the GBT collaboration 2015 – 02 – 03 http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 1
Radiation Hard Optical Link Development of an high speed bidirectional radiation hard optical link: Versatile link project: GBT project: • Opto-electronics • • Radiation hardness ASIC design • • Functionality testing Verifjcation • • Packaging Functionality testing • Packaging GBT GBT Versatile Link FPGA Timing & Trigger Timing & Trigger PD GBTIA GBTX DAQ DAQ GBTX LD GBLD Slow Control Slow Control Custom ASICs On-Detector Ofg-Detector Radiation Hard Electronics Commercial Ofg-The-Shelf (COTS) http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 2
GBTX Chip Set • The GBT chipset comprises: GBTIA GBLD GBTIA GBLD – GBTIA: • 4.8 Gb/s Transimpedance Amplifjer • Amplifjes the weak photo-current detected by the PIN diode – GBLD: • 4.8 Gb/s Laser Driver • Modulates laser current to achieve electro-optical conversion – GBTX: • 4.8 Gb/s Transceiver • Manages the communications between the counting room and the frontend modules GBT – SCA GBTX GBT – SCA GBTX – GBT – SCA • Slow Control Adapter • Experiment control and environment monitoring • GBTIA, GBLD and GBTX: – Have been successfully prototyped – Radiation tolerance proved to > 100 Mrad • GBT – SCA: – Prototypes currently being tested http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 3
Versatile Link • Small Form Factor (SFP) T ransceiver: – Data rate: 5 Gb/s – Wave length: • 850 nm, Multimode • 1310 nm, Single mode – Function: • Point-to-point • Point-to-multipoint • Development of pluggable modules. – T wo versions: • Transceiver ( VTRx ) • Double transmitter ( VTTx ) – Compatible with the commercial counterparts – LC connectors – Length reduced to 43.5 mm – Contains: • The GBTIA & GBLD • Radiation qualifjed PIN diodes and Lasers – Radiation tolerant: • 50 Mrad • 5 x 10 14 n/cm 2 – Prototyping phase concluded: • Prototypes available • Production planed for 2015 • T arget LS2 upgrades http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 4
The GBT System External clock reference Clock[7:0] FE E – P Module o r t e-Link GBTX Phase - Shifter CLK Reference/xPLL E – P o r t FE E Phase – Aligners + Ser/Des for E – Ports – ePLLR P Module o GBTIA r x t DEC/DSCR E – CDR P o r t data-down CLK Manager data-up clock 80, 160 and 320 Mb/s ports GBLD SCR/ENC SER E – P o ePLLT r t x FE E – P Module o r t E – P o r t Confjguration One 80 Mb/s port Control Logic (e-Fuses + reg- Bank) E GBT – SCA – JTAG I2C Slave I2C Master P o r t I2C (light) data JTAG I2C control Port Port clocks http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 5
GBTX Data Bandwidth • The GBTX supports three frame types: – “GBT” Frame – “Wide Bus” Frame – “8B/10B” Frame • “GBT” Mode – User bandwidth: 3.28 Gb/s • Up/down-links • “Wide Bus” and “8B/10B”frames are only supported for the uplink GBT Frame: – The downlink always uses the • Frame Synchronization: “GBT” frame. – DC balanced and “redundant” header • “8B/10B” Mode • Forward Error Correction: – Downlink data 8B/10B encoded – Interleaved Reed-Solomon double – No FEC error correction – User bandwidth: 3.52 Gb/s – 4-bit symbols (RS(15,11)) • “Wide Bus” Mode: – Interleaving: 2 – Error correction capability: – Uplink data scrambled • 2 Interleaving × 2 RS = 4 symbols = – No FEC 16-bits – User bandwidth: 4.48 Gb/s – Code effjciency: 88/120 = 73% http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 6
GBTX Frames GBT Frame (for up and down links) EC G4 G3 G2 G1 G0 H(3:0) IC(1:0) EC(1:0) D(79:64) D(63:48) D(47:32) D(31:16) D(15:0) FEC(31:16) FEC(15:0) Wide Bus Frame (for up-links only) EC G4 G3 G2 G1 G0 G6 G5 H(3:0) IC(1:0) EC(1:0) D(79:64) D(63:48) D(47:32) D(31:16) D(15:0) D(111:96) D(95:80) “Out of order” bit sequence for compatibility with the GBT frame 8B/10B Frame (for up-links only) G6 (not used) G5 (1/2) G4 G3 G2 G1 G0 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B 8B/10B http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 7
GBTX Functionality (1/4) e-Links • 40 bi-directional e-Links – Up to 40 @ 80 Mb/s – Up to 20 @ 160 Mb/s GBTX – Up to 10 @ 320 Mb/s Phase - Shifter CLK Reference/xPLL • e-Port data rate can be set E – P independently for: o r t Phase – Aligners + Ser/Des for E – Ports ePLLR – each group x DEC/DSCR – Input / output ports E – CDR P • o 1 bi-directional e-Link: r t CLK Manager – 80 Mb/s • 40 e-Link clocks (fjxed phase) programmable in frequency: – 40/80/160/320 MHz (per group) SCR/ENC SER – (independently of the bit rate) E – P o ePLLT • r Automatic, semi-automatic or user t x controlled phase alignment of the incoming serial data embedded in the E – P o e-Ports r t Confjguration Control Logic (e-Fuses + reg- – Automatic alignment Bank) • Tracks temperature and voltage variations JTAG I2C Slave I2C Master • Transparent to the user • Works on any type of data: – DC balanced / un-balanced – A few “occasional” transition enough to ensure correct operation http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 8
GBTX Functionality (2/4) e-Links Special cases • 8B/10B mode: – 44 input (max @ 80 Mb/s) GBTX Phase - Shifter CLK Reference/xPLL – 36 output (max @ 80 E Mb/s) – P o r t • (Four outputs reused as Phase – Aligners + Ser/Des for E – Ports ePLLR x inputs) DEC/DSCR E – CDR P o • Wide-Bus mode: r t CLK Manager – 56 input (max @ 80 Mb/s) – 24 output (max @ 80 Mb/s) SCR/ENC • (16 “outputs” reused as SER E inputs) – P o ePLLT r t x e-Links electrical characteristics E – P o r t Confjguration • Drivers: Control Logic (e-Fuses + reg- Bank) – SLVS signaling JTAG I2C Slave I2C Master • Receivers: – SLVS/LVDS signaling http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 9
GBTX Functionality (3/4) Phase-Shifter • 8 independent clocks • Programable in frequency: GBTX Phase - Shifter CLK Reference/xPLL – 40 / 80 / 160 / 320 MHz E – • Programable in phase: P o r t Phase – Aligners + Ser/Des for E – Ports ePLLR – 0 to 360◦ x DEC/DSCR E – Phase resolution: 50 ps – CDR P o r t • (for all frequencies) CLK Manager • Clock driver electrical levels: SCR/ENC SER – SLVS E – P o ePLLT r t Reference clock: x • On package crystal E – P o r t Confjguration • Built-in crystal oscillator Control Logic (e-Fuses + reg- Bank) • Built-in VCXO based PLL JTAG I2C Slave I2C Master (xPLL) • External reference can used as well http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 10
GBTX Functionality (4/4) Chip Control • e-Fuse register bank for burn in confjguration GBTX – Standalone operation Phase - Shifter CLK Reference/xPLL – Ready at power up E – P o r • Dynamic confjguration and t Phase – Aligners + Ser/Des for E – Ports ePLLR control x DEC/DSCR E – CDR – I2C Slave interface P o r t – IC control channel trough the CLK Manager optical link • Watchdog circuit for chip SCR/ENC operation supervision. SER E – P o ePLLT GBLD Control r t x • GBLD dedicated I2C master E – interface P o r t Confjguration Control Logic (e-Fuses + reg- – Copies confjguration burned Bank) in the GBTX into the GBLD at JTAG I2C Slave I2C Master start-up – Allows to program the GBLD either through the IC channel or through the I2C slave port http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 11
GBTX In Numbers • ½ million gates 4.3 mm • Approximately: – 300 8-bit programable registers (all TMR) – 300 8-bit e-Fuse memory • Clock tree (chip wide): – 9 clock trees (all TMR) 4.3 mm – Frequencies: 40/80/160/320 MHz • 7 PLLs: – RX: CDR PLL + Reference PLL (2.4 GHz) – Serializer PLL (4.8 GHz) – Phase-Shifter PLL (1.28 GHz) – xPLL (VCXO based PLL, 80 MHz) – (2x) ePLL (320 MHz) 17 mm • 17 master DLLs: – 9 for phase alignment of the e-links Total height including solder balls: ~3 mm – 8 for clock de-skewing • 56 replica delay lines: – For phase alignment of the e-links • 7 power domains: 17 mm – Serializer (1.5V) – DESerializer (1.5V) – Clock Manager (1.5V) – Phase shifter (1.5V) – Core digital (1.5V) – I/O (1.5V) – Fuses (3.3V) http://cern.ch/proj-gbt Paulo.Moreira@cern.ch 12
GBTX package
The GBTX up-link • Each eLink is associated with a specifjc set of bits in the frame • Front-end modules are thus eLinks: 80 /160 / 320 Mbps “geographically” addressed: Data and clock line (optional) Frontend By being physically connected – Module to an eLink No module address is required Frontend – Module GBTX Frontend GBT-Frame Module 4.8 Gbps optical-fjbre link Frontend IC Control Module GBT-SCA http://cern.ch/proj-gbtd Paulo.Moreira@cern.ch 14
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