Future State-of-the-Art Electrical Interconnect Byungsub Kim* and - - PowerPoint PPT Presentation

future state of the art electrical interconnect
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Future State-of-the-Art Electrical Interconnect Byungsub Kim* and - - PowerPoint PPT Presentation

Future State-of-the-Art Electrical Interconnect Byungsub Kim* and Vladimir Stojanovi Integrated Systems Group Massachusetts Institute of Technology *Currently with Intel Corporation Many-core processor era Tilera 64 core processor 1000


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Integrated Systems Group Massachusetts Institute of Technology

Future State-of-the-Art Electrical Interconnect

Byungsub Kim* and Vladimir Stojanovi *Currently with Intel Corporation

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Many-core processor era

Tilera 64 core processor

1000 cores in the future ?

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Global interconnects for latency

Mesh Flattened Butterfly Clos

Increasing number of cores latency issue. Global NoC interconnects are attractive.

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Nanophotonic on-chip interconnect

Large bandwidth with small energy cost per bit over

long distance

Extra cost

n CMOS compatible fabrication, extra area, energy overhead. n We are keep improving …

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Batten et. al., Micro2009

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The winning interconnects?

electrical repeater nanophotonics

Nanophotonics v.s. electrical repeater Compare bandwidth and power consumption.

?

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The winning interconnects?

electrical repeater nanophotonics

?

electrical equalizer

Equalized interconnects. Consideration on area and

latency.

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Outline

Fair comparison metrics. Trade-off of repeated interconnects. Trade-off of equalized interconnects. Status of equalized electrical

interconnects based on silicon measurement.

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Fair interconnect metrics?

For a given target distance

Data rate density =

(Data rate)/ (cross-sectional width)

Energy per bit Latency In general, we cannot normalize these metrics by

length.

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Trade-off: repeated interconnects

Repeater trade-off: three dimensional surface.

n Wires and circuits are jointly optimized.

KIM D&T 2008 1cm long 32nm technology aggressively scaled (http://ptm.asu.edu)

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Trade off: repeated interconnects

Same energy per bit: same capacitance Larger data rate density : Tsb < Tsa Larger latency : Tdb > Tda

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Trade-off: repeated interconnects

Repeater trade-off: three dimensional surface.

n Wires and circuits are jointly optimized.

KIM D&T 2008 1cm long 32nm technology aggressively scaled (http://ptm.asu.edu)

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Equalized Interconnects

Potentially lower power and higher data

rate than repeaters.

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Evolution of equalized interconnects

2005, 130nm, Rpt. 2005, 130nm, Eq. 2007, 90nm, Rpt. (modeling) 2009, 90nm, Eq. 2007, 90nm, Eq.

Evolution of Eq. Evolution of Rpt.

1-cm links

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Review: equalization in frequency domain

+ + =

Tx: HPF Channel: LPF Rx: HPF Overall: flat higher data rate

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Review: equalization in time domain

No equalization Feed forward equalization (FFE) FFE + decision feedback equalization (DFE)

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Trade-off: equalized interconnect

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Rx can sense small voltage ~ 100mV. Tx swing is adjusted for target eye size (constant). Tx swing is proportional to attenuation. By rule of thumb, energy per bit cost

Sense amplifier

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Review: power consumption of equalization

Kim ICCAD 2007

Power overhead required

n New topologies greatly reduced power overhead.

n Eg.) Kim ISSCC2009, Mensink ISSCC2007, …

Driver power overhead: used be > 50% <25%)

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Trade off: equalized interconnect

Kim ICCAD 2007

Equalized and unequalized pulses corresponding for isolated ‘1’ at Tx and Rx (90nm technology) Tx No Eq. Tx Eq. Rx No Eq. Rx Eq.

Td

For a given data rate

density tareget, latency is fixed.

The channel determines

equalized Tx and Rx waveforms and the proper sampling time Td (latency).

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Trade-off: equalized interconnects

Trade-off curve of equalized interconnect is 3-

dimensional line.

KIM D&T 2008 1cm long 32nm technology aggressively scaled (http://ptm.asu.edu)

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The winning interconnect

Depends on application requirements. In general,

n Rpt. wins in short distance (<5mm) or long distance

applications (>10mm).

n Eq. wins in medium distance (5mm-10mm).

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Current status: equalized interconnects

2-3Gb/s/um with 400fJ/b-600fJ/b over 10mm in 90nm CMOS

ASIC technology.

We can expect further improvement in 22nm high-performance

processor technology.

10mm long 5mm long

Kim JSSC 2010 Mensink ISSCC 2009 Tam VLSI 2009 Seo ISSCC2010 21

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Conclusion

To set the right direction of nanophotonics, we must compare

them to the winning electrical interconnects, either repeated or equalized.

Fair comparison metrics

n data rate density, energy per bit, and latency.

A repeated interconnect trade off is a 3-dimensional surface.

n latency data rate density

Equalized interconnects provide better energy efficiency for the

same performance in many situations than repeated ones.

There is no absolute winner.

n In general, an equalized interconnect is better for 5-10mm distance.

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