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Architecture Measurements Design of 2nd Prototype Summary

Front–end Electronics for Straw Tube Tracker in PANDA Experiment

Dominik Przyborowski, Marek Idzik

AGH University of Science and Technology

PANDA STT Workshop 10 October 2013, Juelich

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Outline

1

Front–end Specification and Architecture

2

Measurements of 1st Prototype

3

Design of 2nd Prototype

4

Summary

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Specification

Features CSP with variable gain and time constant CR–RC2 shaper with variable peaking time Ion tail cancellation circuit with trimming Baseline stabilized by BLH circuit Leading edge discriminator for time and ToT measurements Fast LVDS output Buffered analog output

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Architecture

Preamplifier and Shaper

Schematic diagram

• Features

Variable charge gain: 0.5 – 4 mV/fC Variable preamp time constant: 25 – 800 ns PZC matched to various preamp settings 1st shaper stage with TP in range 10 – 40 ns Input transistor Drain current = 2 mA W/L = 2000µ/0.35µ Transconductance ≈ 26 mS

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Architecture

Tail Cancellation and Output stages

Schematic diagram

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• +
• +
• Tail cancellation

4 modes of operation: τ1 & τ2 TC, only τ1 TC, only τ2 TC, CR–RC2 (no TC) Trimming time constants: τ1 ∈ 3 – 43 ns (6 bits) τ2 ∈ 18 – 511 ns (6 bits)

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Architecture

Baseline Holder

Schematic diagram

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• K

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• K

Components Nonlinear buffer (slew rate limited - OTA0 and C0) High value tunable active resistor for low pass filter

(A. Tajalli, Y. Leblebici, E.J. Brauer, Implementing Ultra-High-Value Floating Tunable CMOS Resistors, Electronics Letters, 2008, pp. 349-350)

Current sink controlling current in last stage feedback

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Architecture

Leading Edge Discriminator

Schematic diagram Stages Two low–gain preamplifing stages Latch stage with histeresis Self–biased amplifier Inverters

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

First prototype basic data

AMS 0.35µm 2P–4M CMOS Process Four channels Channel size: 200×1130 µm2 Power consumption: ∼ 15.5 mW/ch + LVDS ∼ 12 mW ≈ 28 mW/ch Peripherals not yet designed, biasing and thresholds setting externally

Chip size: 1.5 × 1.2 mm2

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Pulse shapes

δ pulse response for 10ns TP settings (CR–RC2 mode – no TC)

1.34 1.36 1.38 1.4 1.42 1.44 1.46 1.48 1.5 1.52 1.54 1.56 10 20 30 40 50 60 70 80 Output voltage (V) Time (ns) Cin = 5.7 (pF) Cin = 23 (pF) Cin = 34 (pF)

Response slower due to layout parasitics and output buffer performance

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Linearity and Gain

Channel modes (CR–RC2 mode – no TC)

1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 50 100 150 200 250 300 350 400 450 Output Voltage (V) Input Charge (fC) Vbaseline = 1.186 (V) K.5

q = 3.8 (mV/fC)

K1

q = 6.9 (mV/fC)

K2

q = 13.2 (mV/fC)

K4

q = 23.4 (mV/fC)

Kpre = 0.5 (mV/fC) Kpre = 1 (mV/fC) Kpre = 2 (mV/fC) Kpre = 4 (mV/fC)

S–curves measurements Channel uniformity (with TC)

200 400 600 800 1000 1200 1400 1600 20 40 60 80 100 120 140 160 Output Voltage (V) Input Charge (fC) K1 = 9.5 (mV/fC) K2 = 10.1 (mV/fC) K3 = 10.1 (mV/fC) K4 = 10.6 (mV/fC) K5 = 9.6 (mV/fC) K6 = 9.9 (mV/fC) K7 = 10.3 (mV/fC) K8 = 10.6 (mV/fC) Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8

Analog buffer output

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Noise

ENC vs input capacitance

0.1 0.2 0.3 0.4 0.5 0.6 0.7 20 40 60 80 100 624 1248 1873 2497 3121 3745 4370 Equivallent Noise Charge (fC) Equivallent Noise Charge (e-) Input capacitance (pF) Kq

pre = 0.5 (mV/fC)

Kq

pre = 1 (mV/fC)

Kq

pre = 2 (mV/fC)

Kq

pre = 4 (mV/fC)

ENC vs peaking time

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 5 10 15 20 25 30 35 40 45 624 936 1248 1561 1873 2185 2497 2809 Equivallent Noise Charge (fC) Equivallent Noise Charge (e-) Peaking time (ns) Kpre = 0.5 (mV/fC) Kpre = 4 (mV/fC)

ENC ≈ 1000 e− for default FE settings (Kpre = 2mV /fC, TP = 10ns and Cin = 25pF)

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Tail cancellation

Responses for Fe55 X–rays

• 20

20 40 60 80 100 120 140 160 180 50 100 150 200 250 Output voltage (mV) Time (ns) non-optimized

• ptimized
• 20

20 40 60 80 100 120 140 160 180 200 400 600 800 1000 1200

High rate

h3

Entries 2001 Mean 361.9 RMS 192.2

100 200 300 400 500 600 1.32 1.34 1.40 1.44 1.48 1.52 1.56 1.60 h3

Entries 2001 Mean 361.9 RMS 192.2

h3 Time (ns) Output Voltage (V) Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Time resolution

Time walk

2 4 6 8 10 20 40 60 80 100 Time walk (ns) Input charge (fC)

Jitter

5 10 15 20 25 30 35 40

• 0.6
• 0.4
• 0.2

0.2 0.4 0.6 Counts Time (ns) σ = 0.14 (ns)

1–2 ns time precision could be obtained by compensating time walk basing on amplitude information

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Time–over–Threshold

50 52 54 56 58 60 62 20 40 60 80 100 Time-over-Threshold (ns) Input charge (fC)

Results achieved for delta pulse and different FEE settings

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Fe55 X–rays spectrums

Amplitude spectrum ToT spectrum

Good separation of Fe55 K–α and escape peaks for both methods

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Baseline

Baseline level vs temperature

1.365 1.366 1.367 1.368 1.369 1.37 25 30 35 40 45 Baseline voltage (V) Temperature (oC)

Measure after output buffer – Vgs and β variations

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Measurement results

Summary of 1st prototype

1st prototype of STT front–end fully functional Variable gain 3 – 24 mV/fC and peaking time ∼ 20 – 40 ns work well ENC ≈ 1000 e− for default conditions (Kpre = 2mV /fC, TP = 10ns and Cin = 25pF) Tail cancellation works and could be trimmed to various types

• f input signals

Readout module with 8 ASICs (32 channels) succesfully used in test-beam The front–end design and performance was presented at TWEPP–2013

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Design of 2nd Prototype

Features not implemented in 1st prototype Lack of DACs for baseline control (high baseline dispersion was expected) Longer TP (18 ns) in post–layout simulations Issues found during tests Saturation of preamplifier for large signals Analog buffer not addapted for high capacitive load Planned improvements Implementation of 8 channels Redesign of preamp/shaper for higher speed (TP=10 ns) DAC addition and BLH modification for uniform baseline Improvement of analog buffer Elimination of saturation for large signals

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Design of 2nd Prototype

Preamplifier and shaper

Planned Modifications Complementary architecture with pseudo Class AB Flipped Voltage Follower DC current compensation circuit Variable charge gain: 1, 2 and 4 mV/fC Response rise time ∼ 5 ns (3× faster)

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Design of 2nd Prototype

Shapers and analog output

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• Planned Modifications

Current buffer to separate 1st shaper stage and tail cancellation (to avoid Tp walking vs TC settings) Improvments of BLH to minimize offset (σ ≈ 5 mV) 2nd shaper stage with high performance Push–Pull buffer

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Design of 2nd Prototype

Simulation results

Preamplifier

572 574 576 578 580 582 584 586 20 40 60 80 100 Output voltage (mV) Time (ns)

Tpeak ≈ 5.5 ns TP ≈ 15 ns in 1st prototype Analog output – δ pulse, CR–RC2

995 1000 1005 1010 1015 1020 1025 10 20 30 40 50 60 70 80 Output voltage (mV) Time (ns)

Tpeak ≈ 10.1 ns TP ≈ 17 ns in 1st prototype

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Design of 2nd Prototype

Simulation results

Baseline dispersion

10 20 30 40 50 60 70 80 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 Counts Baseline Voltage (V) µ = 1.001 (V) σ = 4.5m (V)

Baseline dispersion one order of magnitude less than in 1st prototype 4–bits DAC will be added for fine tunning

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E

Architecture Measurements Design of 2nd Prototype Summary

Summary and plans

Front–end development status 1st prototype of STT front–end fully functional Variable gain 3 – 24 mV/fC and peaking time ∼ 20 – 40 ns work well ENC ≈ 1000 e− for default conditions (Kpre = 2mV /fC, TP = 10ns and Cin = 25pF) Tail cancellation works and could be trimmed to various types of input signals Readout module with 8 ASICs (32 channels) succesfully used in test-beam Future plans New improved front–end design in progress: 8 channels DACs for threshold and baseline settings Faster preamp/shaper Stronger output buffer Better performance for large signals Submission of new prototype planned at the end of this year (if founds available)

Dominik Przyborowski, Marek Idzik Front–end Electronics for Straw Tube Tracker in PANDA E