Fluctuation Smoothing Production Control at IBMs 200mm Wafer - - PowerPoint PPT Presentation

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Fluctuation Smoothing Production Control at IBMs 200mm Wafer - - PowerPoint PPT Presentation

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IEEE/SEMI Advanced Semiconductor Manufacturing Conference Fluctuation Smoothing Production Control at IBMs 200mm Wafer Fabricator James R. Morrison Central Michigan University Department of Engineering and Technology Elizabeth Dews John

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SLIDE 1

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

1

Fluctuation Smoothing Production Control at IBM’s 200mm Wafer Fabricator

James R. Morrison Central Michigan University Department of Engineering and Technology Elizabeth Dews John LaFreniere IBM, Systems and Technology Group

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SLIDE 2

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

2

Presentation Overview

  • IBM’s 200mm wafer fabricator
  • Competing control methodologies
  • Multiple cycle time FSVCT policy
  • Estimation of cycle times
  • Implementation challenges
  • Performance evaluation
  • Concluding remarks
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SLIDE 3

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

3

IBM’s 200mm Fabricator

  • Reentrant process flow – 30 or more

visits to certain tool groups

  • Products

– More than 30 different semiconductor technologies – Dozens of products within each technology

  • Up to 400 stages of processing
  • Over 200 distinct tool groups
  • Production capacity about 1000

wafers/day

  • Cycle time about 40 to 60 days with

production time around 20 days

Tool Group 1 Tool Group 2 Tool Group 3 Tool Group 4 Tool Group 5 Tool Group 6 Tool Group 7 Tool Group 8 Tool Group 9 Tool Group 11 Tool Group 12 Tool Group 10

Lots enter

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SLIDE 4

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

4

Competing Control Methodologies

Objective: Minimize overall cycle time and meet due date targets

Increasing Implementation Effort Roughly Increasing Optimality

Variant of continuous flow manufacturing

Existing policy Produce fixed amount per day Loading changes require updates Prioritization to implement preference

Deterministic finite–horizon mathematical programming

ILOG software product Requires detailed data and setup

Critical ratio (CR)

Due date based policy Considered easy to implement

KANBAN

Finite queue lengths

Fluctuation smoothing for the variation of cycle time (FSVCT)

Reduce variation of cycle time by driving all lots to the same average CT FSVCT and related policies successful in many simulations/implementations

Fluid limit inspired policies

Cycle time optimization Requires optimization and model

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SLIDE 5

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

5

Multiple Cycle Time FSVCT Policy

  • First “law” of queueing: Variation leads to cycle time

– At 95% loading: D/D/1 normalized CT = 1 – At 95% loading: M/D/1 queue normalized CT = 10.5 – Fluctuation Smoothing for the Variation of Cycle Time (FSVCT) Policy [Lu-Ramaswamy-Kumar, 1994]

  • Cycle time expectations for a group of lots g

– Common route, common expected pace – CTg = total expected cycle time – hg(l) = expected remaining cycle time for lot l

  • MCT – FSVCT Slack:

– Serve lot l with the least slack  Drives lots from g to same cycle time

g NOR g

CT CT l l Slack )] ( fab in Time [ : ) ( h   

Expected total cycle time

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SLIDE 6

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

6

Multiple Cycle Time FSVCT Policy

  • MCT – FSVCT Slack:

– Serve lot l with the least slack  Drives lots from g to same cycle time

  • Examples:

Time in Fab hg(l) CTg Slack(l) Lot l1 10 23 30

  • 33

30 CTNOR = -(1.1)CTNOR Lot l2 10 17 30

  • 27

30 CTNOR = -(0.9)CTNOR Lot l3 20 46 60

  • 66

60 CTNOR = -(1.1)CTNOR

g NOR g

CT CT l l Slack )] ( fab in Time [ : ) ( h   

Expected total cycle time

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SLIDE 7

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

7

Estimation of Expected Cycle Times

  • Fundamental parameters for MCT–

FSVCT:

– CTg = total expected cycle time – hg(l) = expected remaining cycle time for lot l

  • Absence of plant model combining:

– Routes – Capacities – Cycle times

  • How to determine cycle times?

– Simulation? Costly to create model and maintain – Measure and use existing CTs – Set some CTs (preferred customers)  determine CT imposed on remaining lots

Tool Group 1 Tool Group 2 Tool Group 3 Tool Group 4 Tool Group 5 Tool Group 6 Tool Group 7 Tool Group 8 Tool Group 9 Tool Group 11 Tool Group 12 Tool Group 10

Lots enter

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SLIDE 8

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

8

Estimation of Expected Cycle Times

  • Little’s Law: lg = Ng / CTg

– Ng is mean number of g lots – CTg is mean cycle time for a g lot

  • Let lots of group g require Pg stages
  • f production

– Aggregate rate of completion of stages of production – Lg = Pg Ng / CTg

  • For groups of lots with similar

production path:

  • Assume holds in the face of control

changes (subject to feasibility)

  • EXAMPLE:
  • Group 1 and group 2 lots are similar
  • Total L = 4500 lot*stages/day
  • Group 1 lots:

– P1 = 300 stages, N1 = 100 lots, CT = 20 – L1 = (300)(100)/(20) = 1500 lot*stages/day

  • Group 2 lots:

– P2 = 300 stages, N2 = 400 lots, CT = ? – L2 = L – L1 = 3000 lot*stages/day = (300)(400)/CT2 – CT2 = 40 days

  • Assuming equality holds  Predict CT for

use in MCT-FSVCT

 

 

 L  L

c g g g g c g g

CT N P :

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SLIDE 9

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

9

Implementation Challenges

  • Cycle time targets must be mutable

– Management directed reprioritization of WIP – Update: CTg  CT’g – Update: hg(l)  h’g(l) – Arrival dates must be updated: a(l)  a’(l) –

  • Patience and maintenance of focus
  • Programming resource allocation
  • Operators need not follow the dictates of the policy

] / ' [ * ] ) ( [ ) ( '

g g CT

CT Now l a Now l a   

Initial Stage Final Stage Current Stage Expected Stage Initial Stage Final Stage Current Stage Expected Stage

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SLIDE 10

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

10

Performance Evaluation

  • Multiple cycle time FSVCT

– Implementation date: April 2005

  • Performance evaluation challenges

– No fabricator cycle time model – Ever changing load and mix – Loading reduction prior and subsequent to implementation – Queueing time consists of roughly 30% of the cycle time

  • Alternative considerations

– Cycle time variation reduction – Variation as a function of cycle time – Throughput as a function of WIP

Cycle Time Performance Curves for Manufacturing Systems

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.2 0.4 0.6 0.8 1 Loading (Utilization) Normalized Cycle Time M/M/1 - Cycle Time M/D/1 - Cycle Time Practical System - Approximate Cycle Time

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SLIDE 11

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

11

Standard Deviation Performance

  • For the same cycle time: M/M/1 has greater standard

deviation of cycle time than M/D/1

  • Does our change in control policy shift the standard

deviation performance of the fabricator?

M/D/1 Standard Deviation is Less than M/M/1 Standard Deviation at Constant Cycle Time

1 2 3 4 5 1 2 3 4 5

Normalized Cycle Time Standard Deviation of Cycle Time

M/M/1-STD M/D/1-STD

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SLIDE 12

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

12

Standard Deviation Performance

  • Reduction in fabricator loading
  • Queueing time about 30% of the cycle time
  • Reduction in standard deviation of cycle time

Normalized Cycle Time (X Factor) Standard Deviation of Normalized Cycle Time After FSVCT - Standard Deviation Before FSVCT - Standard Deviation

Monthly Standard Deviation of Cycle Time: Before and After Implementation of FSVCT

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SLIDE 13

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

13

Throughput and WIP Performance

  • For the same fixed level of work in process (WIP):

– Exponential server has less throughput than deterministic

  • Does our change in control policy shift the throughput

performance of the fabricator?

Throughput as a Function of WIP: Consequences of Randomness

0.2 0.4 0.6 0.8 1 1.2 2 4 6 8 10 Lots in System Mean Throughput (Normalized) Ideal Throughput Mean Throughput: Exponential Service To achieve 90% of maximum throughput, 9 lots in the system

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SLIDE 14

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

14

Throughput and WIP Performance

  • Reduction in work in process (WIP) within fabricator
  • Throughput and WIP reduction observed
  • Low loading regime (30% of cycle time due to queueing)

Wafers in the Fabricator/Tool Completed Daily (Throughput) Total Stages of Production Throughput - Pre-FSVCT Throughput - Post-SVCT Estimated Ideal Throughput

Throughput Performance as a Function of WIP Weekly Data for IBM BTV 200mm

Post-FSVCT

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SLIDE 15

IEEE/SEMI Advanced Semiconductor Manufacturing Conference

May 22-24, 2006 ASMC 2006 – Boston, Massachusetts

15

Concluding Remarks

  • Multiple cycle time FSVCT production control policy implemented in

IBM’s 200mm semiconductor wafer manufacturing facility April 2005

  • Provides:

– Variation smoothing heuristic – Capability to adjust cycle time targets during production – Approximate tool to assess the consequences of prioritization – Control requiring only simple fabricator measurements

  • Dramatically increased functionality coupled with variation reduction
  • Future directions:

– Capacity–state dependent control (incorporate status of bottleneck tools) – WIP–state dependent control