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Flow Lines with Regular Service Times: Evolution of Delay, State Dependent Failures and Semiconductor Wafer Fabrication James R. Morrison KAIST (Korea Advanced Institute of Science and Technology) IEEE CASE 2008 August 23, 2008 Presentation

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James R. Morrison

KAIST (Korea Advanced Institute of Science and Technology)

IEEE CASE 2008 – August 23, 2008

Flow Lines with Regular Service Times:

Evolution of Delay, State Dependent Failures and Semiconductor Wafer Fabrication

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SLIDE 2

IEEE CASE 2008 – Washington, DC August 24, 2008 2

Presentation Overview

 Motivation  Description of flow lines

 Successive bottlenecks  Resettable monotone channel (RMC)

 Delay in an RMC  Delay in a flow line  Application to semiconductor wafer fabrication

 Setups  Batches of wafers (i.e., lots)

 Concluding remarks

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SLIDE 3

IEEE CASE 2008 – Washington, DC August 24, 2008 3

Motivation

 Semiconductor wafer fabrication

 Many cluster tools: Multiple process chambers clustered into a single

chassis

 Photolithography tools

 Models for simulation and throughput analyses

 Expressive (not just a throughput model, allows lot-to-lot interaction)  Practical (e.g., setups, first wafer effect, …)  Want to describe transient and lot-to-lot behavior

 GOAL: Develop expressive and computationally tractable

flow line models

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IEEE CASE 2008 – Washington, DC August 24, 2008 4

System Description: Flow Lines

 M distinct modules: Wafers must receive service from all

modules in order, then the wafer exits the system

 Deterministic (regular) process times: ti in module mi  Manufacturing blocking

 At most one wafer may occupy a module at a given time  If the downstream module is occupied, a wafer must wait to advance

m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12

Wafers Enter Wafers Exit t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12

. . .

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IEEE CASE 2008 – Washington, DC August 24, 2008 5

System Description: Successive Bottlenecks

 Definition: The modules with process time ti > tj, j < i are

termed successive bottlenecks

 Decomposition in terms of these successive bottlenecks  Definition: M consecutive modules are termed a resettable

monotone channel (RMC) if

 tM(w+1) > tM(w) for all wafers until empty, then tM(w+1) > tM(1)  t1 < tM(k) and t1 > tj, j = 2, …, M-1

30 s

10 s 20 s 0 s

40 s

35 s 28 s

60 s 18 s

m2 m3 m6 m9 m1 m4 m7 m5 m8

30 s

10 s 20 s 0 s

40 s

m2 m3 m1 m4 m5

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SLIDE 6

IEEE CASE 2008 – Washington, DC August 24, 2008 6

Wafer Delay in an RMC: Simulation

1

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked)

Time: 0 s

BEGIN SIMULATION

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SLIDE 7

IEEE CASE 2008 – Washington, DC August 24, 2008 7

Wafer Delay in an RMC: Simulation

1

Time: 10 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked)

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SLIDE 8

IEEE CASE 2008 – Washington, DC August 24, 2008 8

Wafer Delay in an RMC: Simulation

1

Time: 20 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked)

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SLIDE 9

IEEE CASE 2008 – Washington, DC August 24, 2008 9

Wafer Delay in an RMC: Simulation

2

Time: 30 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 1

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SLIDE 10

IEEE CASE 2008 – Washington, DC August 24, 2008 10

Wafer Delay in an RMC: Simulation

2

Time: 40 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 1

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SLIDE 11

IEEE CASE 2008 – Washington, DC August 24, 2008 11

Wafer Delay in an RMC: Simulation

2

Time: 50 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 1

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SLIDE 12

IEEE CASE 2008 – Washington, DC August 24, 2008 12

Wafer Delay in an RMC: Simulation

2

Time: 60 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 1 3

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IEEE CASE 2008 – Washington, DC August 24, 2008 13

Wafer Delay in an RMC: Simulation

2

Time: 70 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 1 3

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SLIDE 14

IEEE CASE 2008 – Washington, DC August 24, 2008 14

Wafer Delay in an RMC: Simulation

2

Time: 80 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 1 3

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SLIDE 15

IEEE CASE 2008 – Washington, DC August 24, 2008 15

Wafer Delay in an RMC: Simulation

2

Time: 90 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 1 3 4

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SLIDE 16

IEEE CASE 2008 – Washington, DC August 24, 2008 16

Wafer Delay in an RMC: Simulation

Time: 100 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 2 3 4

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SLIDE 17

IEEE CASE 2008 – Washington, DC August 24, 2008 17

Wafer Delay in an RMC: Simulation

Time: 110 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 2 3 4

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SLIDE 18

IEEE CASE 2008 – Washington, DC August 24, 2008 18

Wafer Delay in an RMC: Simulation

Time: 120 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 2 3 4 5

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SLIDE 19

IEEE CASE 2008 – Washington, DC August 24, 2008 19

Wafer Delay in an RMC: Simulation

Time: 130 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 2 3 4 5

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SLIDE 20

IEEE CASE 2008 – Washington, DC August 24, 2008 20

Wafer Delay in an RMC: Simulation

Time: 140 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 4 5 3

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IEEE CASE 2008 – Washington, DC August 24, 2008 21

Wafer Delay in an RMC: Simulation

Time: 150 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 4 5 3 6

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IEEE CASE 2008 – Washington, DC August 24, 2008 22

Wafer Delay in an RMC: Simulation

Time: 160 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 4 5 3 6

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SLIDE 23

IEEE CASE 2008 – Washington, DC August 24, 2008 23

Wafer Delay in an RMC: Simulation

Time: 170 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 4 5 3 6

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SLIDE 24

IEEE CASE 2008 – Washington, DC August 24, 2008 24

Wafer Delay in an RMC: Simulation

Time: 180 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 4 6 7

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IEEE CASE 2008 – Washington, DC August 24, 2008 25

Wafer Delay in an RMC: Simulation

Time: 190 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 4 6 7

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IEEE CASE 2008 – Washington, DC August 24, 2008 26

Wafer Delay in an RMC: Simulation

Time: 200 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 4 6 7

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IEEE CASE 2008 – Washington, DC August 24, 2008 27

Wafer Delay in an RMC: Simulation

Time: 210 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 4 6 7 8

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IEEE CASE 2008 – Washington, DC August 24, 2008 28

Wafer Delay in an RMC: Simulation

Time: 220 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 6 7 8

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SLIDE 29

IEEE CASE 2008 – Washington, DC August 24, 2008 29

Wafer Delay in an RMC: Simulation

Time: 230 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 6 7 8

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IEEE CASE 2008 – Washington, DC August 24, 2008 30

Wafer Delay in an RMC: Simulation

Time: 240 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 6 7 8 9

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IEEE CASE 2008 – Washington, DC August 24, 2008 31

Wafer Delay in an RMC: Simulation

Time: 250 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 5 6 7 8 9

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IEEE CASE 2008 – Washington, DC August 24, 2008 32

Wafer Delay in an RMC: Simulation

Time: 260 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 6 7 9 8

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SLIDE 33

IEEE CASE 2008 – Washington, DC August 24, 2008 33

Wafer Delay in an RMC: Simulation

Time: 270 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 6 7 9 8 10

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SLIDE 34

IEEE CASE 2008 – Washington, DC August 24, 2008 34

Wafer Delay in an RMC: Simulation

Time: 280 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 6 7 9 8 10

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IEEE CASE 2008 – Washington, DC August 24, 2008 35

Wafer Delay in an RMC: Simulation

Time: 290 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 6 7 9 8 10

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IEEE CASE 2008 – Washington, DC August 24, 2008 36

Wafer Delay in an RMC: Simulation

Time: 300 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 7 8 10 9 11

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IEEE CASE 2008 – Washington, DC August 24, 2008 37

Wafer Delay in an RMC: Simulation

Time: 310 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 7 8 10 9 11

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IEEE CASE 2008 – Washington, DC August 24, 2008 38

Wafer Delay in an RMC: Simulation

Time: 320 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 7 8 10 9 11

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IEEE CASE 2008 – Washington, DC August 24, 2008 39

Wafer Delay in an RMC: Simulation

Time: 330 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 7 8 10 9 11

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IEEE CASE 2008 – Washington, DC August 24, 2008 40

Wafer Delay in an RMC: Simulation

Time: 340 s

t1 = 30 s t2 = 10 s t3 = 20 s t4 = 0 s t5 = 40 s

= Processing = Delayed (blocked) 8 9 10 11 12

END SIMULATION

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IEEE CASE 2008 – Washington, DC August 24, 2008 41

Wafer Delay in an RMC: Time Line – Wafer 1

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IEEE CASE 2008 – Washington, DC August 24, 2008 42

Wafer Delay in an RMC: Time Line – Wafer 2

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IEEE CASE 2008 – Washington, DC August 24, 2008 43

Wafer Delay in an RMC: Time Line – Wafer 3

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IEEE CASE 2008 – Washington, DC August 24, 2008 44

Wafer Delay in an RMC: Time Line – Wafer 4

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IEEE CASE 2008 – Washington, DC August 24, 2008 45

Wafer Delay in an RMC: Time Line – Wafer 5

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IEEE CASE 2008 – Washington, DC August 24, 2008 46

Wafer Delay in an RMC: Time Line – Wafer 6

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IEEE CASE 2008 – Washington, DC August 24, 2008 47

Wafer Delay in an RMC: Time Line – Wafer 7

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IEEE CASE 2008 – Washington, DC August 24, 2008 48

Wafer Delay in an RMC: Time Line – Wafer 8

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IEEE CASE 2008 – Washington, DC August 24, 2008 49

Wafer Delay in an RMC: Time Line – Wafer 9

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IEEE CASE 2008 – Washington, DC August 24, 2008 50

Wafer Delay in an RMC: Time Line – Wafer 10

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IEEE CASE 2008 – Washington, DC August 24, 2008 51

Wafer Delay in an RMC: Time Line – Wafer 11

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IEEE CASE 2008 – Washington, DC August 24, 2008 52

Wafer Delays in an RMC: Key Behaviors (1)

 di(w) = delay wafer w experiences in module i (waiting for i+1)  Y(w) = d1(w) + d2(w) + … + dM(w)  Theorem: If a wafer w experiences delay

 There is a first module in which delay occurs, call it j*

dj(w) = 0, j < j* 0 < dj*(w) < tM(w-M+j*) – tj* dj(w) = tM(w-M+j) – tj , j > j*

No delay until j* Maximum delay possible after j*

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IEEE CASE 2008 – Washington, DC August 24, 2008 53

Wafer Delays in an RMC: Key Behaviors (2)

 di(w) = delay wafer w experiences in module i (waiting for i+1)  Y(w) = d1(w) + d2(w) + … + dM(w)  Theorem: There is a recursion to calculate Y(w+1)

 With Y(w+1), we can readily calculate module delays for wafer w+1

       

   

w d a a w Y S w Y

w w M M 1 1 1 , 1

, max , min , max 1        

 

       

1 1 1

, max 1

      

w w

a w d w d a w d

 

   

l k j j M l k

S :

,

maximum in-channel delay in mk, …, ml

where

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IEEE CASE 2008 – Washington, DC August 24, 2008 54

Wafer Delays in a Flow Line: Key Behaviors

 Successive bottleneck decomposition: Flow line consists of

successive RMCs

 Each RMC behaves exactly like an RMC in isolation!  Delay in a flow line is essentially described by the previous equations!

 Theorem: In each RMC, if a wafer w experiences delay

 There is a first module in the RMC in which delay occurs, call it j*

There is no delay in the RMC before j* After j*, the delay is the maximum possible

30 s

10 s 20 s 0 s

40 s

35 s 28 s

60 s 18 s

m2 m3 m6 m9 m1 m4 m7 m5 m8

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IEEE CASE 2008 – Washington, DC August 24, 2008 55

Application to Semiconductor Wafer Fabrication (1)

 Detailed characterization of wafer flow allows us to

incorporate practical features

 Setups may be required between lots – often, all modules prior to a

specific module must be empty of wafers before it can begin

 Temporary pause in the bottleneck module (e.g., change of setting)  Batches of wafers grouped into lots (typically 25 wafers)

 Additional key features

 Buffer modules can be incorporated using tj = 0  For identical parallel modules

50 s 50 s 50 s 150 s 150 s 150 s

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IEEE CASE 2008 – Washington, DC August 24, 2008 56

Application to Semiconductor Wafer Fabrication (2)

 Flow line delay evolution allows us to treat these problems  Setups (state dependent)

 Require that all modules prior to a specific module be empty  Use knowledge of delay to determine when this module empties!

 Wafer lots

 Rather than evolving the delay from wafer to wafer  Can evolve the delay experienced by groups of wafers  Requires less computation to study lot level behavior (while retaining

information necessary to determine the internal state of the flow line)

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IEEE CASE 2008 – Washington, DC August 24, 2008 57

Computational Complexity (1)

 Consider a flow line with

 M modules (bottleneck B be the last one; simple evolution after B)  There are s successive bottlenecks, bs = B and bs1 is the

module number of the previous successive bottleneck

 Simulate for W wafers, L is the number of wafers per lot

 Theorem: Computational complexity of the various approaches

Max/Min Operations Addition Operations Multiplication Operations Max/Min Operations Addition Operations Multiplication Operations Basic Evolution Equations W(M+1) W(M+1) Evolution of All Successive Bottlenecks W(5s-2) W(16s-15) 3M+2s-7+b(s)-b(s-1) Evolution of the Final Channel Alone 8W 12W 3b(s)-2b(s-1)-2 Evolution of Final Channel Alone with Batch Arrivals W(11/L) W(19/L) W(6/L) 3b(s)-2b(s-1)-2 Recursion Initialization

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IEEE CASE 2008 – Washington, DC August 24, 2008 58

Computational Complexity (2)

 Example: Computational complexity

 Suppose there are M = 36 modules (including the buffer modules)  L = 24 wafers per lot  The bottleneck is the 20th module (bs = 20) and bs1 = 8  There are 5 successive bottlenecks

Max/Min Operations Addition Operations Multiplication Operations Max/Min Operations Addition Operations Multiplication Operations Basic Evolution Equations 37W 37W Evolution of All Successive Bottlenecks 23W 65W 123 Evolution of the Final Channel Alone 8W 12W 42 Evolution of Final Channel Alone with Batch Arrivals 0.458W 0.792W 0.25W 42 Recursion Initialization

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IEEE CASE 2008 – Washington, DC August 24, 2008 59

Concluding Remarks

 Flow lines can serve to model cluster tools

 Must ignore robot behavior but can incorporate transient behavior

 Flow line can be decomposed into successive bottlenecks

 Each pair of successive bottlenecks forms an RMCs  Wafer delay in an RMC is structured and predictable  Delay is flow line is structured and predictable

 Application to semiconductor wafer fabrication

 Can be used for expressive simulation with reduced complexity

 Future directions

 Steady state throughput analysis (with state dependent failures)  Multiple products