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Flow Lines with Regular Service Times: Evolution of Delay, State Dependent Failures and Semiconductor Wafer Fabrication James R. Morrison KAIST (Korea Advanced Institute of Science and Technology) IEEE CASE 2008 August 23, 2008 Presentation

  1. Flow Lines with Regular Service Times: Evolution of Delay, State Dependent Failures and Semiconductor Wafer Fabrication James R. Morrison KAIST (Korea Advanced Institute of Science and Technology) IEEE CASE 2008 – August 23, 2008

  2. Presentation Overview  Motivation  Description of flow lines  Successive bottlenecks  Resettable monotone channel (RMC)  Delay in an RMC  Delay in a flow line  Application to semiconductor wafer fabrication  Setups  Batches of wafers (i.e., lots)  Concluding remarks August 24, 2008 2 IEEE CASE 2008 – Washington, DC

  3. Motivation  Semiconductor wafer fabrication  Many cluster tools: Multiple process chambers clustered into a single chassis  Photolithography tools  Models for simulation and throughput analyses  Expressive (not just a throughput model, allows lot-to-lot interaction)  Practical (e.g., setups, first wafer effect, …)  Want to describe transient and lot-to-lot behavior  GOAL: Develop expressive and computationally tractable flow line models August 24, 2008 3 IEEE CASE 2008 – Washington, DC

  4. System Description: Flow Lines . . . Wafers Wafers m 1 m 2 m 3 m 4 m 5 m 6 m 7 m 8 m 9 m 10 m 11 m 12 Enter Exit t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12  M distinct modules: Wafers must receive service from all modules in order, then the wafer exits the system  Deterministic (regular) process times: t i in module m i  Manufacturing blocking  At most one wafer may occupy a module at a given time  If the downstream module is occupied, a wafer must wait to advance August 24, 2008 4 IEEE CASE 2008 – Washington, DC

  5. System Description: Successive Bottlenecks m 1 m 2 m 3 m 4 m 5 m 6 m 7 m 8 m 9 30 s 10 s 20 s 0 s 40 s 35 s 28 s 60 s 18 s  Definition: The modules with process time t i > t j , j < i are termed successive bottlenecks  Decomposition in terms of these successive bottlenecks  Definition: M consecutive modules are termed a resettable monotone channel (RMC) if  t M (w+1) > t M (w) for all wafers until empty, then t M (w+1) > t M (1)  t 1 < t M (k) and t 1 > t j , j = 2, …, M -1 m 1 m 2 m 3 m 4 m 5 30 s 10 s 20 s 0 s 40 s August 24, 2008 5 IEEE CASE 2008 – Washington, DC

  6. Wafer Delay in an RMC: Simulation BEGIN SIMULATION = Processing = Delayed (blocked) Time: 0 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 1 August 24, 2008 6 IEEE CASE 2008 – Washington, DC

  7. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 10 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 1 August 24, 2008 7 IEEE CASE 2008 – Washington, DC

  8. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 20 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 1 August 24, 2008 8 IEEE CASE 2008 – Washington, DC

  9. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 30 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 2 1 August 24, 2008 9 IEEE CASE 2008 – Washington, DC

  10. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 40 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 2 1 August 24, 2008 10 IEEE CASE 2008 – Washington, DC

  11. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 50 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 2 1 August 24, 2008 11 IEEE CASE 2008 – Washington, DC

  12. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 60 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 3 2 1 August 24, 2008 12 IEEE CASE 2008 – Washington, DC

  13. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 70 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 3 2 1 August 24, 2008 13 IEEE CASE 2008 – Washington, DC

  14. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 80 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 3 2 1 August 24, 2008 14 IEEE CASE 2008 – Washington, DC

  15. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 90 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 4 3 2 1 August 24, 2008 15 IEEE CASE 2008 – Washington, DC

  16. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 100 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 4 3 2 August 24, 2008 16 IEEE CASE 2008 – Washington, DC

  17. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 110 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 4 3 2 August 24, 2008 17 IEEE CASE 2008 – Washington, DC

  18. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 120 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 5 4 3 2 August 24, 2008 18 IEEE CASE 2008 – Washington, DC

  19. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 130 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 5 4 3 2 August 24, 2008 19 IEEE CASE 2008 – Washington, DC

  20. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 140 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 5 4 3 August 24, 2008 20 IEEE CASE 2008 – Washington, DC

  21. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 150 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 6 5 4 3 August 24, 2008 21 IEEE CASE 2008 – Washington, DC

  22. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 160 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 6 5 4 3 August 24, 2008 22 IEEE CASE 2008 – Washington, DC

  23. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 170 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 6 5 4 3 August 24, 2008 23 IEEE CASE 2008 – Washington, DC

  24. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 180 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 7 6 5 4 August 24, 2008 24 IEEE CASE 2008 – Washington, DC

  25. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 190 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 7 6 5 4 August 24, 2008 25 IEEE CASE 2008 – Washington, DC

  26. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 200 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 7 6 5 4 August 24, 2008 26 IEEE CASE 2008 – Washington, DC

  27. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 210 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 8 7 6 5 4 August 24, 2008 27 IEEE CASE 2008 – Washington, DC

  28. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 220 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 8 7 6 5 August 24, 2008 28 IEEE CASE 2008 – Washington, DC

  29. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 230 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 8 7 6 5 August 24, 2008 29 IEEE CASE 2008 – Washington, DC

  30. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 240 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 9 8 7 6 5 August 24, 2008 30 IEEE CASE 2008 – Washington, DC

  31. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 250 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 9 8 7 6 5 August 24, 2008 31 IEEE CASE 2008 – Washington, DC

  32. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 260 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 9 8 7 6 August 24, 2008 32 IEEE CASE 2008 – Washington, DC

  33. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 270 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 10 9 8 7 6 August 24, 2008 33 IEEE CASE 2008 – Washington, DC

  34. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 280 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 10 9 8 7 6 August 24, 2008 34 IEEE CASE 2008 – Washington, DC

  35. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 290 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 10 9 8 7 6 August 24, 2008 35 IEEE CASE 2008 – Washington, DC

  36. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 300 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 11 10 9 8 7 August 24, 2008 36 IEEE CASE 2008 – Washington, DC

  37. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 310 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 11 10 9 8 7 August 24, 2008 37 IEEE CASE 2008 – Washington, DC

  38. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 320 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 11 10 9 8 7 August 24, 2008 38 IEEE CASE 2008 – Washington, DC

  39. Wafer Delay in an RMC: Simulation = Processing = Delayed (blocked) Time: 330 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 11 10 9 8 7 August 24, 2008 39 IEEE CASE 2008 – Washington, DC

  40. Wafer Delay in an RMC: Simulation END SIMULATION = Processing = Delayed (blocked) Time: 340 s t 1 = 30 s t 2 = 10 s t 3 = 20 s t 4 = 0 s t 5 = 40 s 12 11 10 9 8 August 24, 2008 40 IEEE CASE 2008 – Washington, DC

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