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Fault Insertion using IEEE1149.x Implementation of Fault Insertion - - PowerPoint PPT Presentation
Fault Insertion using IEEE1149.x Implementation of Fault Insertion - - PowerPoint PPT Presentation
EBTW05 EBTW05 Fault Insertion using IEEE1149.x Implementation of Fault Insertion in a commercial product and required bsdl support Ken Filliter National Semiconductor Pete Collins JTAG Technologies EBTW 2005, Tallinn, Estonia Slide 1
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Fault Insertion Example
VCC
Inserted Fault 1
Fail Pass Pass Pass
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Fault Insertion Example
VCC
1
Fail
Inserted Fault
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Fault Insertion - Approaches
Faults can be injected in hardware by adding switches.
Limited # of locations – concern about effect on mission circuit – custom approach may not always be repeatable.
Faults can be injected in Si with proprietary techniques.
Drawbacks of proprietary approach – documentation, 3rd party support,etc.
Faults can be injected using software – various ways.
Not necessarily a true test of the “hardware”. Can be labour intensive.
Faults can be injected using boundary scan (IEEE1149.x)
Needs to be described in bsdl and readily imported by 3rd parties.
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Comparison of Methods
?
EASY and INEXPENSIVE
?
No Effect on Mission Random Plentiful IEEE1149.x Software Proprietary Si Hardware
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Comparison of Methods
EASY and INEXPENSIVE No Effect on Mission Random Plentiful IEEE1149.x Software Proprietary Si Hardware
WITH TOOL SUPPORT !
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Fault Insertion Si Implementation
Must not interfere with the signal path ! Must be compatible with IEEE1149.1, .4 and .6. Should be as versatile as possible:
Multiple independent insertion points, possible on inputs and outputs, single ended or differential, stuck-at high or low.
Small Silicon area Should not slow down or in any other way restrict or impede
- ther uses of IEEE1149.x.
Must be Readily Described in bsdl and Friendly to 3rd party Tools !
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Design Implementation
Mux Fault Insertion Value with Test Data
No additional delays in the signal path
Establish new Register with Stuck-at Information
Avoid additional bits in the B/S register – no effect on test duration. Easiest to describe in bsdl.
Use 2 bits per pin to describe stuck-at condition.
Stuck-at data is set to 0 or 1 Stuck-at control determines if that pin will receive stuck-at data.
“Stuck-at” IEEE1149.x instruction loaded to create stuck-at
AND of TAP Stuck-at signal and pin specific stuck-at control bit will force stuck-at data value on targeted pins.
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StuckAt Output Cells
C U C U Mission Dot 1/6 Mode 1 StuckAt From TAP StuckAt
Data On/Off
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StuckAt Input Cells
Pad C U C U Dot 1 StuckAt From TAP StuckAt
Data On/Off
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dot 1, dot 6 and Fault Insertion
Next BSC
PAD
Next Stuckat
CORE
Prev BSC
Prev Stuckat STUCK-AT A C E X T E S T
TAP dot 1 dot 6 STUCK-AT Value STUCK-AT Control Next BSC
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Fault Insertion Tool Support
For ‘fault insertion’ to be used effectively it must be supported by ‘third party’ boundary-scan tools vendors. For ‘fault insertion’ to be easily implemented within software it must be described within the Boundary Scan Description Language (BSDL) file for the device. It must be described in a format that can be easily read by any third party BSDL parser software.
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Stuck-at Data Register Description
The Stuck-at DATA Register order can be described simply in a table format, but this is not readable for standard BSDL parsers
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BSDL Extensions
The IEEE 1149.1 standard does allow users to define their own extensions to the BSDL language to include new syntax for additional functionality The extensions must be declared explicitly within the BSDL file before they can be defined, or within the user-defined package description, declared by the ‘use’ statement. The BSDL Extension attributes for the ‘fault insertion’ capability are:
attribute SA_REGISTER of SCAN90CP02 : entity is
- - num cell port function safe [ccell disval rslt]
"0 (BC_1, * ,CONTROLR , 0)," & "1 (SA_DATA, OUT_POS1 ,INTERNAL , X, 0, 0)," & "2 (BC_1, * ,CONTROLR , 0)," & "3 (SA_DATA, OUT_POS0 ,INTERNAL , X, 2, 0)," & "4 (BC_1, * ,CONTROLR , 0)," & "5 (SA_DATA, PEM11 ,INTERNAL , X, 4, 0)," & "6 (BC_1, * ,CONTROLR , 0)," & "7 (SA_DATA, PEM10 ,INTERNAL , X, 6, 0)," & "8 (BC_1, * ,CONTROLR , 0)," & "9 (SA_DATA, PEM01 ,INTERNAL , X, 8, 0)," & "10 (BC_1, * ,CONTROLR, 0)," & "11 (SA_DATA, PEM00 ,INTERNAL , X, 10, 0)," & "12 (BC_1, * ,CONTROLR, 0)," & "13 (SA_DATA, EN_N1 ,INTERNAL , X, 12, 0)," & "14 (BC_1, * ,CONTROLR, 0)," & "15 (SA_DATA, EN_N0 ,INTERNAL , X, 14, 0)," & "16 (BC_1, * ,CONTROLR, 0)," & "17 (SA_DATA, SEL1 ,INTERNAL , X, 16, 0)," & "18 (BC_1, * ,CONTROLR, 0)," & "19 (SA_DATA, SEL0 ,INTERNAL , X, 18, 0)," ; attribute SA_REGISTER of SCAN90CP02 : entity is
- - num cell port function safe [ccell disval rslt]
"0 (BC_1, * ,CONTROLR , 0)," & "1 (SA_DATA, OUT_POS1 ,INTERNAL , X, 0, 0)," & "2 (BC_1, * ,CONTROLR , 0)," & "3 (SA_DATA, OUT_POS0 ,INTERNAL , X, 2, 0)," & "4 (BC_1, * ,CONTROLR , 0)," & "5 (SA_DATA, PEM11 ,INTERNAL , X, 4, 0)," & "6 (BC_1, * ,CONTROLR , 0)," & "7 (SA_DATA, PEM10 ,INTERNAL , X, 6, 0)," & "8 (BC_1, * ,CONTROLR , 0)," & "9 (SA_DATA, PEM01 ,INTERNAL , X, 8, 0)," & "10 (BC_1, * ,CONTROLR, 0)," & "11 (SA_DATA, PEM00 ,INTERNAL , X, 10, 0)," & "12 (BC_1, * ,CONTROLR, 0)," & "13 (SA_DATA, EN_N1 ,INTERNAL , X, 12, 0)," & "14 (BC_1, * ,CONTROLR, 0)," & "15 (SA_DATA, EN_N0 ,INTERNAL , X, 14, 0)," & "16 (BC_1, * ,CONTROLR, 0)," & "17 (SA_DATA, SEL1 ,INTERNAL , X, 16, 0)," & "18 (BC_1, * ,CONTROLR, 0)," & "19 (SA_DATA, SEL0 ,INTERNAL , X, 18, 0)," ; attribute SA_REGISTER_LENGTH of SCAN90CP02 : entity is 20; attribute SA_REGISTER_LENGTH of SCAN90CP02 : entity is 20; attribute SA_REGISTER_LENGTH: BSDL_EXTENSION; attribute SA_REGISTER: BSDL_EXTENSION;
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Similarities to Boundary-Scan Data Register
num cell port function safe [ccell disval] “0 (BC_1, * , CONTROLR, 0), " & “1 (SA_DATA, OUT_POS1, INTERNAL , X, 0, 0),” & “2 (BC_1, * , CONTROLR, 0), " & “3 (SA_DATA, OUT_POS0, INTERNAL , X, 2, 0),” & num cell port function safe [ccell disval] “0 (BC_1, * , CONTROLR, 0), " & “1 (SA_DATA, OUT_POS1, INTERNAL , X, 0, 0),” & “2 (BC_1, * , CONTROLR, 0), " & “3 (SA_DATA, OUT_POS0, INTERNAL , X, 2, 0),” & num cell port function safe [ccell disval rslt] “4 (AC_1, OUT_POS1, OUTPUT3, X, 8, 0, Z),” & "8 (BC_1, * , CONTROL, 0), ” & num cell port function safe [ccell disval rslt] “4 (AC_1, OUT_POS1, OUTPUT3, X, 8, 0, Z),” & "8 (BC_1, * , CONTROL, 0), ” &
The format described for the new ‘stuck- at’ data register is similar to that of the standard boundary-scan data register description. In this example an AC_1 cell (num 4) is described as a 3-state output cell, which is disabled by a logic ‘0’ value in control cell (num 8), placing the o/p driver in highZ as detailed by the rslt field.
CELL 8 CELL 4
3-STATE OUTPUT
The stuck-at data register description defines a new cell SA_DATA which is used to seed the stuck-at data value. The CONTROLR cell is used to disable the stuck-at condition with a disable value of ‘0’; each SA_DATA cell has a dedicated CONTROR cell.
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SA_DATA cell description
package Fault_Insertion_v1_2005 is use STD_1149_1_2001.all; attribute SA_REGISTER_LENGTH: BSDL_EXTENSION; attribute SA_REGISTER: BSDL_EXTENSION; constant SA_DATA : Cell_Info; -- Stuck_At Fault Value end Fault_Insertion_v1_2005; package body Fault_Insertion_v1_2005 is use STD_1149_1_2001.all; -- Refer to BSDL definitions
- - Captures ‘Seed’ values in the SA_Data FF
constant SA_DATA : Cell_Info:= ((INTERNAL, SA, Zero), (INTERNAL, SA_PRELOAD, Zero), (INTERNAL, SA, One), (INTERNAL, SA_PRELOAD, One), (INTERNAL, SA, X), (INTERNAL, SA_PRELOAD, X), (INTERNAL, SA, CAP), (INTERNAL, SA_PRELOAD, CAP)); end Fault_Insertion_v1_2005; package Fault_Insertion_v1_2005 is use STD_1149_1_2001.all; attribute SA_REGISTER_LENGTH: BSDL_EXTENSION; attribute SA_REGISTER: BSDL_EXTENSION; constant SA_DATA : Cell_Info; -- Stuck_At Fault Value end Fault_Insertion_v1_2005; package body Fault_Insertion_v1_2005 is use STD_1149_1_2001.all; -- Refer to BSDL definitions
- - Captures ‘Seed’ values in the SA_Data FF
constant SA_DATA : Cell_Info:= ((INTERNAL, SA, Zero), (INTERNAL, SA_PRELOAD, Zero), (INTERNAL, SA, One), (INTERNAL, SA_PRELOAD, One), (INTERNAL, SA, X), (INTERNAL, SA_PRELOAD, X), (INTERNAL, SA, CAP), (INTERNAL, SA_PRELOAD, CAP)); end Fault_Insertion_v1_2005;
The SA_DATA cell description defines an array of cell data records containing 3 fields that define:
- CELL type
- BSCAN instruction
- CAPture data source
In the SA_DATA cell example, two instructions; SA and SA_PRELOAD allow access to the internal SA_DATA cells, whose values can be set to Zero, One, unknown or the previously CAPtured value.
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Capture FF Capture FF Stuck Stuck-
- at Data source
at Data source Zero, One, X or CAP Zero, One, X or CAP SA_DATA cell SA_DATA cell CONTROLR cell CONTROLR cell Logic Logic ‘ ‘0 0’ ’ in CONTROLR in CONTROLR cell disables the stuck cell disables the stuck-
- at
at condition from being condition from being muxed muxed through to the device pin. through to the device pin. Seeded stuck Seeded stuck-
- at value
at value The StuckAt signal The StuckAt signal is asserted when either is asserted when either the SA or SA_PRELOAD the SA or SA_PRELOAD instructions are latched instructions are latched
SA_DATA & CONTROLR cell descriptions
This diagram describes a combination of standard BC_1 cell, 1149.6 and StuckAt data cells. The StuckAt data register comprises
- f a number of sequential SA_DATA
and CONTROLR cells
TDI TDI TDO TDO
PAD CORE M U X 3 1149.1 1149.6 Stuck-At M U X 2 M U X 1
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Stuck-at GUI
This proposal details how a fault insertion register can be described within the BSDL language, so that 3rd party boundary-scan tools can easily generate the bit streams for selected seeded fault conditions The GUI is just an example of how the stuck-at faults can be seeded for specific injection sites. NOTE:- in this example only one injection site at a time can be seeded with a stuck-at fault for a selected device.
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