Efficient implementation of a spectrum scanner on a software-defined - - PowerPoint PPT Presentation

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Efficient implementation of a spectrum scanner on a software-defined - - PowerPoint PPT Presentation

Jan 10, 2023 159 likes •380 views

Efficient implementation of a spectrum scanner on a software-defined radio platform Franois Quitin, Riccardo Pace Universit libre de Bruxelles (ULB), Belgium 1 Context and objectives Regulators need to detect abusive usage of RF spectrum

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SLIDE 1

1

Efficient implementation of a spectrum scanner

  • n a software-defined radio platform

François Quitin, Riccardo Pace

Université libre de Bruxelles (ULB), Belgium

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SLIDE 2
  • Lots of technicians driving around on all kind of missions

 Use (reasonably) cheap hardware to do opportunistic scanning

  • How to use SDRs to do (pseudo)-realtime spectrum scanning?

– USRP-N210 – Single-board host computer (e.g. Raspberry Pi form factor) – No user intervention

Context and objectives

2

Regulators need to detect abusive usage of RF spectrum

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SLIDE 3
  • http://www.ni.com/white-paper/13882/en/
  • « Spectrum analyzer with USRP, GNU Radio and MATLAB »

http://www.av.it.pt/conftele2009/papers/114.pdf

  • https://github.com/Edgarware/USRP_Spec_Analyzer
  • …

Problems with these implementations?

– Scanning bandwidth may be larger than USRP bandwidth – Fully software-based (Python, Labview, C++), so hard to do real-time

  • n low-weight host

 Solution: implement the spectrum scanner on the USRP FPGA !

– Use software for scan coordination and data recording

Context and objectives

3

What’s wrong with existing codes ?

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SLIDE 4
  • Overall system design

– Intro to FPGA: difference with μC – Spectrum scanner design

  • FPGA design

– FFT module – Square magnitude module – Energy detection module – Data synchronizer module

  • Software design

– Usefull low-level UHD commands – Retuning and streaming – GUI with gnuplot-iostream

  • Some results
  • Demo time!

Outline

4

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SLIDE 5

What is an FPGA …

5

… and why can it be faster than a microcontroller?

  • Executes 1 instruction / cycle
  • Serial processing
  • Compilation: converts HLL to micro-

instructions

  • Limited by duration of execution
  • HLL: C++, Python, …
  • Processes N insctructions / cycle
  • Parallel processing
  • Synthesis and P&R: converts « HLL » to

inter-connection diagram

  • Limited by size of circuitry
  • « HLL »: VHDL or Verilog
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SLIDE 6

The FPGA in the USRP

  • Digital up- and down conversion
  • Decimation/interpolation
  • Formating of samples for UHD drivers

6

Does some basic stuff, but still some space left !

Default FPGA image Flip Flops 42% 4-input LUT 65% Slices 82% DSP48A 24% RAM16BWER 32%

Decim Interp CIC DDC DUC UHD Network Driver Command & Control Data Streaming 32 bit RISC processor FPGA – Xilinx Spartan 3A-DSP from ADC to DAC to/from Ethernet

Hardware elements available in the FPGA

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SLIDE 7

Spectrum scanner design

  • FPGA to perform CPU-intensive task
  • Software to coordinate retuning of carrier frequency and log data

7

Mixed FPGA-software architecture

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SLIDE 8
  • Overall system design

– Intro to FPGA: difference with μC – Spectrum scanner design

  • FPGA design

– FFT module – Square magnitude module – Energy detection module – Data synchronizer module

  • Software design

– Usefull low-level UHD commands – Retuning and streaming – GUI with gnuplot-iostream

  • Some results
  • Demo time!

Outline

8

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SLIDE 9

FPGA design

  • Modules that can be cascaded
  • 2 inputs and outputs for each module

– One for the actual data – One that indicates if data is valid

  • Two versions of the Energy Detection Module

– Fixed threshold (set manually from software) – Automatic threshold (mostly automatic, partial manual setting possible)

9

Detailled FPGA architecture

FFT |Y|2 ENERGY DETECTION MODULE DATA SYNCH MODULE

x[31:0] {I,Q} X[31:0] {I,Q} SQM[31:0] Y[31:0] {D,|Y|2[30:0]} Y[31:0] {D,|Y|2[30:0]} strobe_in dv_fft dv_sqm dv_Y strobe_out

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SLIDE 10

FPGA design

  • FFT module

– 1024-point FFT (not configurable)

10

Details of the different modules

FFT |Y|2 ENERGY DETECTION MODULE DATA SYNCH MODULE

x[31:0] {I,Q} X[31:0] {I,Q} SQM[31:0] Y[31:0] {D,|Y|2[30:0]} Y[31:0] {D,|Y|2[30:0]} strobe_in dv_fft dv_sqm dv_Y strobe_out

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SLIDE 11

FPGA design

  • Energy detection module

𝑗=1

𝑁

𝑍 2 > 𝜇 ? – Fixed threshold: set manually by user from software – Automatic threshold: 𝜇 = 𝜇∗ + 𝛽𝐸𝑥𝑗𝑜𝑒𝑝𝑥 with 𝐸𝑥𝑗𝑜𝑒𝑝𝑥 =

𝑙=𝑜

𝑜+𝑁 𝑍 𝑙 2

𝑙=1

𝑂

𝑍 𝑙

2/𝑂 11

Details of the different modules

FFT |Y|2 ENERGY DETECTION MODULE DATA SYNCH MODULE

x[31:0] {I,Q} X[31:0] {I,Q} SQM[31:0] Y[31:0] {D,|Y|2[30:0]} Y[31:0] {D,|Y|2[30:0]} strobe_in dv_fft dv_sqm dv_Y strobe_out

Average energy over 10MHz-window Energy over current subwindow

N-point FFT size-M subwindow

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SLIDE 12

FPGA design

  • Data synchronizer module

– Readapt the rate of samples to USRP sample rate – Ratio between USRP sample rate and fclock (=100 MHz) has to be an integer value – Design fully compatible with host UHD drivers

12

Details of the different modules

FFT |Y|2 ENERGY DETECTION MODULE DATA SYNCH MODULE

x[31:0] {I,Q} X[31:0] {I,Q} SQM[31:0] Y[31:0] {D,|Y|2[30:0]} Y[31:0] {D,|Y|2[30:0]} strobe_in dv_fft dv_sqm dv_Y strobe_out

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SLIDE 13

FPGA design

  • Our design is very cheap in ressource utilization !

13

Ressource utilization of our additional blocks

Default FPGA image Fixed threshold Automatic threshold Flip Flops 42% +3% +4% 4-input LUT 65% +3% +4% Slices 82% +2% +4% DSP48A 24% +7% +9% RAM16BWER 32% +12% +14%

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SLIDE 14
  • Overall system design

– Intro to FPGA: difference with μC – Spectrum scanner design

  • FPGA design

– FFT module – Square magnitude module – Energy detection module – Data synchronizer module

  • Software design

– Usefull low-level UHD commands – Retuning and streaming – GUI with gnuplot-iostream

  • Some results
  • Demo time!

Outline

14

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SLIDE 15

Software design

  • Set FPGA register from host side (threshold, subwindow size, …)
  • Specify time of command (retune of carrier frequency)

15

Some usefull low-level UHD commands

// set threshold of the energy detector module usrp->set_user_register(TH_ADDRESS,threshold,0); // set the command in time usrp->set_command_time(cmpd_time[i]); t_result[i] = usrp->set_rx_freq(tune_request[i]);

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SLIDE 16

Software design: re-tuning and streaming

  • With this laptop: 250 ms for scanning 1 GHz band w/o overflows

16

Send future retune commands while streaming

… for k=0 to k=7 do set command time @ cmd_time[k] tune_request[k] rx stream command @ cmd_time[k]+delta end for while (1) do receive samples k++ set command time @ cmd_time[k] tune_request[k] rx stream command @ cmd_time[k]+delta end while Retune lock time, typically 1 ms

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SLIDE 17

Software design: light-weight GUI

  • Low refresh rate to avoid hogging CPU
  • Data is also saved to a log file

17

Using gnuplot-iostream

SQM.dat detection.dat

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SLIDE 18
  • Overall system design

– Intro to FPGA: difference with μC – Spectrum scanner design

  • FPGA design

– FFT module – Square magnitude module – Energy detection module – Data synchronizer module

  • Software design

– Usefull low-level UHD commands – Retuning and streaming – GUI with gnuplot-iostream

  • Some results
  • Demo time!

Outline

18

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SLIDE 19

Some results in the lab

  • Bluetooth + Multicarrier signal

19

when connecting signal generator to USRP

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SLIDE 20

Some results outside the lab

20

Scanning for FM stations

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SLIDE 21

Some results right here

  • Demo of GSM and 3G spectrum scan
  • Code available on Github

https://github.com/fquitin/energy_detection_system

  • What’s in the code?

– FPGA source code – FPGA images, flashable on the USRP – Host C++ source code and CMake files – Some Matlab scripts with testbenches and postprocessing scripts

21

Demo time !