Effective Power/Ground Plane Decoupling for PCB Dr. Bruce - - PowerPoint PPT Presentation

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Effective Power/Ground Plane Decoupling for PCB Dr. Bruce - - PowerPoint PPT Presentation

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Effective Power/Ground Plane Decoupling for PCB Dr. Bruce Archambeault IBM Distinguished Engineer IEEE Fellow IBM Research Triangle Park, NC Barch@us.ibm.com October 2007 IEEE IEEE Power Plane Noise Control Ground Bounce October

slide-1
SLIDE 1

Effective Power/Ground Plane Decoupling for PCB

  • Dr. Bruce Archambeault

IBM Distinguished Engineer IEEE Fellow

IBM Research Triangle Park, NC Barch@us.ibm.com October 2007

IEEE IEEE

slide-2
SLIDE 2

October 2007

  • Dr. Bruce Archambeault

2

“Ground Bounce”

Power Plane Noise Control

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SLIDE 3

October 2007

  • Dr. Bruce Archambeault

3

Power/Ground-Reference Plane Noise

  • Must consider TWO Major Factors

– EMC -- Reduce noise along edge of board from IC somewhere else – Functionality -- Provide IC with sufficient charge

  • Decoupling strategies are FULL of Myths

– Consider the physics – Don’t forget Inductance!

slide-4
SLIDE 4

October 2007

  • Dr. Bruce Archambeault

4

Source of Power/Ground-Reference Plane Noise

  • Power requirements from IC during

switching

  • Critical Net currents routed through via
slide-5
SLIDE 5

October 2007

  • Dr. Bruce Archambeault

5

Power Bus Spectrum Clock Driver IDT74FCT807

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SLIDE 6

October 2007

  • Dr. Bruce Archambeault

6

Noise Injected between Planes Due to Critical Net Through Via

Signal Via I/O Pin/Via 30 cm 20 cm

FR4 r=4.2 Loss tan=0.02

slide-7
SLIDE 7

October 2007

  • Dr. Bruce Archambeault

7

Transfer Function from Via to I/O Pin

Transfer Function From Via-to-Via 20x30cm Board

  • 70
  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

1.E+08 1.E+09 1.E+10 Frequency (Hz) Transfer Function (dB) 5 mil Seperation 10 mil Seperation 15 mil Seperation 25 mil Seperation 35 mil Seperation

slide-8
SLIDE 8

October 2007

  • Dr. Bruce Archambeault

8

Decoupling Must be Analyzed in Different Ways for Different Functions

  • EMC

– Resonance big concern – Requires STEADY-STATE analysis

  • Frequency Domain

– Transfer function analysis

  • Eliminate noise along edge of board due to

ASIC/IC located far away

slide-9
SLIDE 9

October 2007

  • Dr. Bruce Archambeault

9

Decoupling Must be Analyzed in Different Ways for Different Functions

  • Provide Charge to ASIC/IC

– Requires TRANSIENT analysis – Charge will NOT travel from far corners of the board fast enough – Local decoupling capacitors dominate – Impedance at ASIC/IC pins important

slide-10
SLIDE 10

October 2007

  • Dr. Bruce Archambeault

10

Steady-State Analysis

  • Measurements and Simulations
  • Test Board with Decoupling capacitors

every 1” square

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SLIDE 11

October 2007

  • Dr. Bruce Archambeault

11 5” 1” 9” 10” 1” 3” 6” 9” 11” 12” Figure 1

Test Board Ports

#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15

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SLIDE 12

October 2007

  • Dr. Bruce Archambeault

12

S21 Used for Decoupling “Goodness”

  • Ratio of Power ‘out’ to power ‘in’
  • Better Indicator of EMI noise transmission

across board

  • Also used to validate simulations
slide-13
SLIDE 13

October 2007

  • Dr. Bruce Archambeault

13 Measured S21 for 12" x 10" PC Board Between Power/Ground Planes with No Decoupling Capacitors (Measured Center to Corner)

  • 80
  • 70
  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 Frequency (Hz) S21 (dB)

Board Capacitance Dominates Physical Board Size Resonances Dominate

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SLIDE 14

October 2007

  • Dr. Bruce Archambeault

14

Test Board Decoupling Capacitor Placement for 25 .01 uf Caps

Possible Cap Location Populated Cap Locations

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SLIDE 15

October 2007

  • Dr. Bruce Archambeault

15

Test Board Decoupling Capacitor Placement for 51 .01 uf Caps

Possible Cap Location Populated Cap Locations

slide-16
SLIDE 16

October 2007

  • Dr. Bruce Archambeault

16 Measured S21 for 12" x 10" PC Board Between Power/Ground Planes with Various Amounts of Decoupling Capacitors (Measured Center to Corner)

  • 100
  • 90
  • 80
  • 70
  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) S21 (dB) No Caps 25 Caps 50 Caps 99 Caps

Measured S21 for 12" x 10" PC Board Between Power/Ground Planes with Various Amounts of Decoupling Capacitors (Measured Center to Corner)

  • 100
  • 90
  • 80
  • 70
  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) S21 (dB) No Caps 25 Caps 50 Caps 99 Caps

slide-17
SLIDE 17

October 2007

  • Dr. Bruce Archambeault

17

S21 Between Port #8 and Port #1 on Test Board With Various Amounts of .01 uf Decoupling Capacitors

  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) S21 (dB) No Caps 25 Caps 51 Caps 99 Caps

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SLIDE 18

October 2007

  • Dr. Bruce Archambeault

18

1.00E+6 1.00E+7 1.00E+8 1.00E+9 1.00E+10

Freq (Hz) 0.1 1 10 100 1000 10000 |Z| (Ohms)

0.01uF 22pF 0.01uF in parallel with 22pF

Cap Impedance

slide-19
SLIDE 19

October 2007

  • Dr. Bruce Archambeault

19

Test Board Decoupling Capacitor Placement for 41 22pf Caps (In Addition to 99 .01uf Caps)

Possible Cap Location Populated Cap Locations

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SLIDE 20

October 2007

  • Dr. Bruce Archambeault

20

S21 Between Port #8 and Port #1 on Test Board With 99 .01 uf Decoupling Capacitors and Various Amounts of 22pf Capacitors Added

  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) S21 (dB) 9 22pf Caps 17 22pf Caps 21 22pf Caps 33 22pf Caps 41 22pf Caps 99 22pf Caps 99 Caps

slide-21
SLIDE 21

October 2007

  • Dr. Bruce Archambeault

21

Measured Comparison of Multiple and Single Value Decoupling Capacitor Strategies

  • 100
  • 90
  • 80
  • 70
  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09 Frequency (Hz) S21 Transfer Function (dB) No Caps 99 0.01 uF Caps 0.01 uF and 330 pF Caps

slide-22
SLIDE 22

October 2007

  • Dr. Bruce Archambeault

22

Comparison of Model and Measured Data for 10" x 12" Board 99 caps -- alternating .01uF and 330pF

  • 100.0
  • 90.0
  • 80.0
  • 70.0
  • 60.0
  • 50.0
  • 40.0
  • 30.0
  • 20.0
  • 10.0

0.0 0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 Frequency (Hz) S21 (dB) CIAO - .01uF & 330 pF Measured

slide-23
SLIDE 23

October 2007

  • Dr. Bruce Archambeault

23

S21 Transfer Function for Different Value Capacitors Center-to-Corner 10" x 12" Board

  • 80
  • 70
  • 60
  • 50
  • 40
  • 30
  • 20
  • 10

0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09 Frequency (Hz) S21 (dB) 99 .01uF caps 99 0.1uF caps 99 0.33uF caps 99 Caps (0.01uF and 330pF) 99 2nh shorts

slide-24
SLIDE 24

October 2007

  • Dr. Bruce Archambeault

24

Voltage Distribution @ 350 MHz .01uF and 330pF Case (Source in

Center)

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SLIDE 25

October 2007

  • Dr. Bruce Archambeault

25

Voltage Distribution @ 750 MHz .01uF and 330pF Case (Source in

Center)

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SLIDE 26

October 2007

  • Dr. Bruce Archambeault

26

Voltage Distribution @ 950 MHz .01uF and 330pF Case (Source in

Center)

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SLIDE 27

October 2007

  • Dr. Bruce Archambeault

27

Decoupling Capacitor Mounting

  • Keep as to planes as close to capacitor

pads as possible

Height above Planes Via Separation

Inductance Depends

  • n Loop AREA
slide-28
SLIDE 28

October 2007

  • Dr. Bruce Archambeault

28

Decoupling Capacitor Mounting

  • Keep as to planes as close to capacitor

pads as possible

Capacitor IC Capacitor Connection Inductance Loop IC Connection Inductance Loop Plane Inductance Loop

slide-29
SLIDE 29

October 2007

  • Dr. Bruce Archambeault

29

Via Configuration Can Change Inductance

Via Capacitor Pads SMT Capacitor

The “Good” The “Bad” The “Ugly” Really “Ugly” Better Best

slide-30
SLIDE 30

October 2007

  • Dr. Bruce Archambeault

30 Comparison of Decoupling Capacitor Impedance 100 mil Between Vias & 10 mil to Planes

0.01 0.1 1 10 100 1000 1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) Impedance (ohms) 1000pF 0.01uF 0.1uF 1.0uF

slide-31
SLIDE 31

October 2007

  • Dr. Bruce Archambeault

31

Via Seperation (mils) Inductance (nH) Impedance @ 1 GHz (ohms)

20 .06 .41 40 0.21 1.3 60 0.36 2.33 80 0.5 3.1 100 0.64 4.0 150 1.0 6.23 200 1.4 8.5 300 2.1 12.69 400 2.75 17.3 500 3.5 21.7

Comparison of Decoupling Capacitor Via Separation Distance Effects

0.1 uF Capacitor

10 mils Via Separation

slide-32
SLIDE 32

October 2007

  • Dr. Bruce Archambeault

32

Example Connection Inductance Values

2.07 nH 2.4 nH 4.3 nH 4.2 nH 0603 + 2*160mil 1.5 nH 2.1 nH 3.15 nH 3.3 nH 0603 + 2*100mil 0.8 nH 1.1 nH 1.74 nH 2.3 nH 0603 + 2*10mil 2.5 nH 3.5 nH 5.1 nH 5.1 nH 0805 + 2*160mil 2.0 nH 3 nH 4.3 nH 4.1 nH 0805 + 2*100mil 1.38 nH 2 nH 3.1 nH 3.0 nH 0805 + 2*10mil Simple rect loop (10 mils to plane) Complex Formula (10 mils to plane) Simple rect loop (20 mils to plane) Complex Formula (20 mils to plane) Spacing between Vias

Fan, Jun, Wei Cui, James L. Drewniak, Thomas Van Doren, and James L. Knighten, “Estimating the Noise Mitigating Effect of Local Decoupling in Printed Circuit Boards,” IEEE Trans. on Advanced Packaging, Vol. 25, No. 2, May 2002, pp. 154-165. Knighten, James L., Bruce Archambeault, Jun Fan, Samuel Connor, James L. Drewniak, “PDN Design Strategies: II. Ceramic SMT Decoupling Capacitors – Does Location Matter?,” IEEE EMC Society Newsletter, Issue No. x, Winter 2006, pp. 56-67. (www.emcs.org) Sources for complex formula:

slide-33
SLIDE 33

October 2007

  • Dr. Bruce Archambeault

33

Transient Analysis

(Time Limited)

  • Provide charge to ASIC/IC
  • Inductance dominates impedance

– Loop area 1st order effect

  • Traditional analysis not accurate

enough

slide-34
SLIDE 34

October 2007

  • Dr. Bruce Archambeault

34

switch IC load IC driver VDC GND CL VCC Z0, vp GND IC load IC driver VCC VCC charge

logic 0-1

Z0, vp shoot-thru current IC load IC driver GND VCC 0 V discharge

logic 1-0

Z0, vp shoot- thru current

Current in IC During Logic Transitions (CMOS)

slide-35
SLIDE 35

October 2007

  • Dr. Bruce Archambeault

35

Typical PCB Power Delivery

GND VCC

DC/DC converter (Power source)

GND VCC

IC load

VCC GND

SMT capacitors

VCC GND

IC driver

VCC GND

electrolytic capacitor

VCC GND

slide-36
SLIDE 36

October 2007

  • Dr. Bruce Archambeault

36

Equivalent Circuit for Power Current Delivery to IC

switch VDC Ltrace Lps Lbulk Cbulk Lvia CSMT Cplanes

connector and wiring capacitor leads electrolytic capacitors via interconnect SMT capacitors VCC/GND plane

IC load

PCB wiring DC/DC converter

slide-37
SLIDE 37

October 2007

  • Dr. Bruce Archambeault

37

Traditional Analysis #1

  • Use impedance of capacitors in parallel

Impedance to IC power/gnd pins ESR1 ESR4 ESR3 ESR2 ESL1 ESL4 ESL3 ESL2 1uF .001uF 0.01uF

  • 0. 1uF

No Effect of Distance Between Capacitors and IC Included!

slide-38
SLIDE 38

October 2007

  • Dr. Bruce Archambeault

38

Traditional Impedance Calculation for Four Decoupling Capacitor Values

0.01 0.1 1 10 100 1000

1.00E+07 1.00E+08 1.00E+09 Frequency (Hz) Impedance (ohms) .1uF .01uF .001uF .0001uF All in Parallel

slide-39
SLIDE 39

October 2007

  • Dr. Bruce Archambeault

39

Traditional Analysis #2

  • Calculate loop area – Traditional loop

Inductance formulas

– Which loop area? Which size conductor

Impedance to IC power/gnd pins ESR1 ESR4 ESR3 ESR2 ESL1+Ld1 1uF .001uF 0.01uF

  • 0. 1uF

ESL2+Ld2 ESL3+Ld3 ESL4+Ld4

Over Estimates L and Ignores Distributed Capacitance

slide-40
SLIDE 40

October 2007

  • Dr. Bruce Archambeault

40

More Accurate Model Includes Distributed Capacitance

Distributed capacitors Intentional Decoupling Capacitors Distributed capacitors IC Power Pin Intentional Decoupling Capacitors

slide-41
SLIDE 41

October 2007

  • Dr. Bruce Archambeault

41

Distributed Capacitance Schematic

Loop L

Capacitance

ESR Distributed Capacitance Intentional Capacitor

Source

Note: L increases as distance from source increases Loop L

Capacitance

ESR Distributed Capacitance Intentional Capacitor

Source Source

Note: L increases as distance from source increases

slide-42
SLIDE 42

October 2007

  • Dr. Bruce Archambeault

42

Effect of Distributed Capacitance

  • Can NOT be calculated/estimated using

traditional capacitance equation

  • Displacement current amplitude changes

with position and distance from the source

slide-43
SLIDE 43

October 2007

  • Dr. Bruce Archambeault

43

Displacement Current 500 MHz via @450 mils from Source

slide-44
SLIDE 44

October 2007

  • Dr. Bruce Archambeault

44

Need to Find the Real Effect of Decoupling Capacitor Distance

  • Perfect decoupling capacitor is a via

between planes

  • FDTD simulation to find the effect of

shorting via distance from source

  • Vary spacing between planes, distance

to via, frequency, etc

slide-45
SLIDE 45

October 2007

  • Dr. Bruce Archambeault

45 Impedance of Shorting Via vs. Frequency Four Via Case (20 mil Seperation Between Plates)

0.1 1 10 100 1.E+08 1.E+09 1.E+10 Frequency (Hz) Impedance (ohms) 20mils 40mils 50mils 60mils 70mils 80mils 90mils 100mils 120mils 130mils 140mils 150mils 160mils 180mils 200mils 220mils 240mils 250mils 350mils 450mils

slide-46
SLIDE 46

October 2007

  • Dr. Bruce Archambeault

46

Impedance Result

  • Linear with frequency (on log scale)
  • Looks like an inductance only!
  • Consider this inductance an Apparent

Inductance

  • Apparent inductance is constant with

frequency

slide-47
SLIDE 47

October 2007

  • Dr. Bruce Archambeault

47 Apparent Inductance for One Shorting Via Case 20 mil Plate Separation

0.2 0.4 0.6 0.8 1 1.2 1.E+08 1.E+09 1.E+1 Frequency (Hz) Inductance (nH) 50mils 110mils 120mils 200mils 250mils 350mils 450mils

slide-48
SLIDE 48

October 2007

  • Dr. Bruce Archambeault

48

Formulas to Predict Apparent Inductance

) 1592 . 2774 . ( ) ( ) 0403 . 1192 . ( ) 1763 . 2848 . ( ) ( ) 0447 . 1242 . ( ) 1943 . 2948 . ( ) ( ) 0492 . 1307 . ( ) 2675 . 2609 . ( ) ( ) 0654 . 1336 . ( + − + − = + − + − = + − + − = + − + − =

− − − −

s dist Ln s L s dist Ln s L s dist Ln s L s dist Ln s L

via four via three via two via

  • ne

s = separation between plates (mils/10) dist = distance to via

slide-49
SLIDE 49

October 2007

  • Dr. Bruce Archambeault

49

Lapparent

LIC Lcap

IC Capacitor

Power Gnd

Lapparent

ESR

Lcap + LIC

Nominal Capacitance

Source

True Impedance for Decoupling Capacitor

slide-50
SLIDE 50

October 2007

  • Dr. Bruce Archambeault

50

Impedance Calculation with Apparent Inductance for Four Decoupling Capacitor Values

0.01 0.1 1 10 1.E+07 1.E+08 1.E+09 Frequency (Hz) Impedance (ohms) Case1 Case2 Case3 Traditional Calculation Cap Value Distance to Cap from IC Case 1 Case 2 Case 3 0.1 uF 800mils 1200mils 1500mils 0.01 uF 600mils 900mils 1100mils 0.001uF 400mils 700mils 800mils 0.0001uF 200mils 400mils 400mils

slide-51
SLIDE 51

October 2007

  • Dr. Bruce Archambeault

51

Effect of Distributed Capacitance

  • Can NOT be calculated/estimated using

traditional capacitance equation

  • Displacement current amplitude changes with

position and distance from the source

  • Following examples use cavity resonance

technique (EZ-PowerPlane)

– Frequency Domain to compare to measurements – Time Domain using SPICE circuit from cavity resonance analysis

slide-52
SLIDE 52

October 2007

  • Dr. Bruce Archambeault

52

Parameters for Comparison to Measurements

  • Dielectric thickness = 35 mils
  • Dielectric constant = 4.5, Loss tan = 0.02
  • Copper conductivity = 5.8 e7 S/m
slide-53
SLIDE 53

October 2007

  • Dr. Bruce Archambeault

53

Measured vs Model (MoM) S21 for 12" x 10" PC Power/gnd with 25 .01uF caps Position 8-to-1

  • 50
  • 40
  • 30
  • 20
  • 10

1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) S21 (dB) No Caps - Measured EZ-PP No Caps

slide-54
SLIDE 54

October 2007

  • Dr. Bruce Archambeault

54 Measured vs Model (EZ-PP) S21 for 12" x 10" PC Power/gnd with 25 .01uF caps Position 8-to-1

  • 100.0
  • 90.0
  • 80.0
  • 70.0
  • 60.0
  • 50.0
  • 40.0
  • 30.0
  • 20.0
  • 10.0

0.0 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) S21 (dB) Measured EZ-PP 25 caps

slide-55
SLIDE 55

October 2007

  • Dr. Bruce Archambeault

55 Measured vs Model (EZ-PP) S21 for 12" x 10" PC Power/gnd with 95 .01uF caps Position 8-to-1

  • 100.0
  • 90.0
  • 80.0
  • 70.0
  • 60.0
  • 50.0
  • 40.0
  • 30.0
  • 20.0
  • 10.0

0.0 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) S21 (dB) 95 Caps - Measured 95 Caps - EZ-PP

slide-56
SLIDE 56

October 2007

  • Dr. Bruce Archambeault

56

Impedance at Port #1 Single 0.01 uF Capacitor at Various Distances (35mil Dielectric)

  • 40
  • 30
  • 20
  • 10

10 20 30 1.0E+07 1.0E+08 1.0E+09 1.0E+10

Frequency (Hz) Impedance (dBohms) no caps 300 mils 500 mils 700 mils 1000 mils

slide-57
SLIDE 57

October 2007

  • Dr. Bruce Archambeault

57 Z11 Phase Comparison as Capacitor distance Varies for 35 mils FR4 ESL = 0.5nH

  • 2
  • 1.5
  • 1
  • 0.5

0.5 1 1.5 2 1.0E+06 1.0E+07 1.0E+08 1.0E+09 Frequency (Hz) Phase (rad)

100 mils 200 mils 300 mils 400 mils 1000 mils 2000 mils

slide-58
SLIDE 58

October 2007

  • Dr. Bruce Archambeault

58 Impedance at Port #1 Single 0.01 uF Capacitor at Various Distances (10mil Dielectric)

  • 50
  • 40
  • 30
  • 20
  • 10

10 20 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) Impedance (dBohms) no caps 300 mils 500 mils 700 mils 1000 mils

slide-59
SLIDE 59

October 2007

  • Dr. Bruce Archambeault

59

Cavity Resonance (EZ-PowerPlane) Equivalent Circuit for HSPICE

Lii Ljj Lij N00i N01i Nmni Nmnj N01j N00j C0 C0 C0 G00 G01 Gmn L01 Lmn

Port i Port j Port n

slide-60
SLIDE 60

October 2007

  • Dr. Bruce Archambeault

60 Impedance Comparison (EZ-PP vs HSPICE) at Port #1 Single 0.01 uF Capacitor at Various Distances (10mil Dielectric)

  • 50
  • 40
  • 30
  • 20
  • 10

10 20 1.0E+07 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) Impedance (dBohms) 300 mils 300 mils (HSPICE) 1000 mils 1000 mils (HSPICE)

slide-61
SLIDE 61

October 2007

  • Dr. Bruce Archambeault

61 Current Source Pulse for Simulated IC Power/GND 750 ps Rise/Fall

  • 0.2

0.2 0.4 0.6 0.8 1 1.2 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Current (amps)

slide-62
SLIDE 62

October 2007

  • Dr. Bruce Archambeault

62 Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp) Single Capacitor (with 2 nH) at Various Distances (Fullwave Simulation)

  • 1.5
  • 1
  • 0.5

0.5 1 1.5 2 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Level (volts) 750ps Rise, 35 mil planes,1uF @ 10mils 750ps Rise, 35 mil planes, 1uF @ 400mils 750ps Rise, 35 mil planes,1uF @ 800mils 750ps Rise, 35 mil planes,1uF @ 1200mils 750ps Rise, 35 mil planes,1uF @ 1600mils

slide-63
SLIDE 63

October 2007

  • Dr. Bruce Archambeault

63 Time Domain Current through Capacitor From Simulated IC Power/GND (1 amp) Single Capacitor (with 2nH) at Various Distances

  • 400
  • 350
  • 300
  • 250
  • 200
  • 150
  • 100
  • 50

50 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Current (milliamps) 750ps Rise, 35 mil planes,1uF @ 10mils 750ps Rise, 35 mil planes,1uF @ 400mils 750ps Rise, 35 mil planes,1uF @ 800mils 750ps Rise, 35 mil planes,1uF @ 1200mils 750ps Rise, 35 mil planes,1uF @ 1600mils

slide-64
SLIDE 64

October 2007

  • Dr. Bruce Archambeault

64 Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp) Single Capacitor (with No L) at Various Distances

  • 2
  • 1.5
  • 1
  • 0.5

0.5 1 1.5 2 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Level (volts) 750ps Rise, 35 mil planes,1uF @ 10mils 750ps Rise, 35 mil planes,1uF @ 400mils 750ps Rise, 35 mil planes,1uF @ 800mils 750ps Rise, 35 mil planes,1uF @ 1200mils 750ps Rise, 35 mil planes,1uF @ 1600mils

slide-65
SLIDE 65

October 2007

  • Dr. Bruce Archambeault

65 Time Domain Current through Capacitor From Simulated IC Power/GND (1 amp) Single Capacitor (with no L) at Various Distances

  • 1200
  • 1000
  • 800
  • 600
  • 400
  • 200

200 400 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Current (milliamps) 750ps Rise, 35 mil planes,1uF @ 10mils 750ps Rise, 35 mil planes,1uF @ 10mils 750ps Rise, 35 mil planes,1uF @ 800mils 750ps Rise, 35 mil planes,1uF @ 1200mils 750ps Rise, 35 mil planes,1uF @ 1600mils

slide-66
SLIDE 66

October 2007

  • Dr. Bruce Archambeault

66 Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp) Single Capacitor with Various Capacitor Connection Inductance

  • 0.4
  • 0.3
  • 0.2
  • 0.1

0.1 0.2 0.3 0.4 0.5 0.6 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Time (ns) Level (volts)

750ps Rise, 10 mil planes, 1uF @ 400mils 750ps Rise, 10 mil planes, (2nH) 1uF @ 400mils 750ps Rise, 10 mil planes, (1nH) 1uF @ 400mils

slide-67
SLIDE 67

October 2007

  • Dr. Bruce Archambeault

67 Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp) Single Capacitor with Various Capacitor Connection Inductance

  • 1.5
  • 1
  • 0.5

0.5 1 1.5 2 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Level (volts) 750ps Rise, 10 mil planes, 1uF @ 400mils 750ps Rise, 10 mil planes, (2nH) 1uF @ 400mils 750ps Rise, 35 mil planes,1uF @ 400mils 750ps Rise, 35 mil planes,(2nH) 1uF @ 400mils

slide-68
SLIDE 68

October 2007

  • Dr. Bruce Archambeault

68 Maximum Time Domain Noise Voltage Across Simulated IC Power/GND Pin Single Capacitor at Various Distances (Fullwave Simulation)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 200 400 600 800 1000 1200 1400 1600 1800 Distance (mils) Voltage (volts) 750 ps Rise, 10 mil planes,1uF, 2 nH 750 ps Rise, 10 mil planes,1uF, 1 nH 750 ps Rise, 10 mil planes,1uF, 0.5 nH 750 ps Rise, 10 mil planes,1uF, No L

slide-69
SLIDE 69

October 2007

  • Dr. Bruce Archambeault

69 Maximum Time Domain Noise Voltage Across Simulated IC Power/GND Pin Single Capacitor at Various Distances (Fullwave Simulation)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 200 400 600 800 1000 1200 1400 1600 1800 Distance (mils) Voltage (volts) 1 ns Rise, 10 mil planes,1uF, 2 nH 1 ns Rise, 10 mil planes,1uF, 1 nH 1 ns Rise, 10 mil planes,1uF, 0.5 nH 1 ns Rise, 10 mil planes,1uF, No L

slide-70
SLIDE 70

October 2007

  • Dr. Bruce Archambeault

70 Maximum Time Domain Noise Voltage Across Simulated IC Power/GND Pin Single Capacitor at Various Distances (Fullwave Simulation)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 200 400 600 800 1000 1200 1400 1600 1800 Distance (mils) Voltage (volts) 750 ps Rise, 35 mil planes,1uF, 2 nH 750 ps Rise, 35 mil planes,1uF, 1 nH 750 ps Rise, 35 mil planes,1uF, 0.5 nH 750 ps Rise, 35 mil planes,1uF, No L

slide-71
SLIDE 71

October 2007

  • Dr. Bruce Archambeault

71 Maximum Time Domain Noise Voltage Across Simulated IC Power/GND Pin Single Capacitor at Various Distances (Fullwave Simulation)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 200 400 600 800 1000 1200 1400 1600 1800 Distance (mils) Voltage (volts) 1 ns Rise, 35 mil planes,1uF, 2 nH 1 ns Rise, 35 mil planes,1uF, No L 1 ns Rise, 35 mil planes,1uF, 0.5 nH 1 ns Rise, 35 mil planes,1uF, 1 nH

slide-72
SLIDE 72

October 2007

  • Dr. Bruce Archambeault

72 Maximum Voltage vs Distance to Capacitor for 1 ns Rise/fall time 0.01 uF Capacitor with 0.5 nH ESL and 30 mOhm ESR

0.2 0.4 0.6 0.8 1 1.2 1.4 200 400 600 800 1000 1200 1400 1600 1800 2000 Distance From Capacitor (mils) Maximum Voltage at source (volts) 35 mil FR4 10 mil FR4 2 mil FR4 1 mil FR4 0.5 mil FR4

slide-73
SLIDE 73

October 2007

  • Dr. Bruce Archambeault

73

So Far……

  • Frequency domain simulations not
  • ptimum for charge delivery decoupling

calculations (phase not considered)

  • Time domain simulations using single

pulse of current indicate limited capacitor location effect

– Connection inductance of capacitor much higher than inductance between planes – Charge delivered only from the planes

slide-74
SLIDE 74

October 2007

  • Dr. Bruce Archambeault

74

Charge Depletion

  • IC draws charge from planes
  • Capacitors will re-charge planes

– Location does matter!

slide-75
SLIDE 75

October 2007

  • Dr. Bruce Archambeault

75

Model for Plane Recharge Investigations

Port2 Port2 (4,5) (4,5) Port1 Port1 (8,7) (8,7) a = 12 a = 12 b = 10 b = 10 d = 35 mil d = 35 mil Cdec Cdec (4.05,5) (4.05,5) Decoupling Capacitor : C = 1uF ESR = 30mOhm ESL = 0.5nH

5 . 4 =

r

ε

DC voltage used to DC voltage used to charge the power charge the power plane plane Vdc Vdc I input I input Port3 Port3 (4,4.95) (4,4.95) Port2 Port2 (4,5) (4,5) Port1 Port1 (8,7) (8,7) a = 12 a = 12 b = 10 b = 10 d = 35 mil d = 35 mil Cdec Cdec (4.05,5) (4.05,5) Decoupling Capacitor : C = 1uF ESR = 30mOhm ESL = 0.5nH

5 . 4 =

r

ε

DC voltage used to DC voltage used to charge the power charge the power plane plane Vdc Vdc I input I input Port3 Port3 (4,4.95) (4,4.95)

Port 2 represents IC current draw

slide-76
SLIDE 76

October 2007

  • Dr. Bruce Archambeault

76

Charge Between Planes vs.. Charge Drawn by IC

Board total charge : C*V = 3.5nF*3.3V = 11nC Pulse charge 5A peak : I*dt/2 = (1ns*5A)/2=2.5nC

slide-77
SLIDE 77

October 2007

  • Dr. Bruce Archambeault

77

Triangular pulses (5 Amps Peak)

slide-78
SLIDE 78

October 2007

  • Dr. Bruce Archambeault

78

(a) (b)

Noise Voltage from Inductive Effect

  • f Current Draw

Current pulses too small to see charge depletion effects in this time scale

slide-79
SLIDE 79

October 2007

  • Dr. Bruce Archambeault

79

Charge Depletion Voltage Drop

2 4 6 8 10 1 1.5 2 2.5 3 3.5 4 Time [ns] Vplane [V] Ls = 1nH Ls = 10 nH Ls = 50 nH

slide-80
SLIDE 80

October 2007

  • Dr. Bruce Archambeault

80

Charge Depletion vs. Capacitor Distance

slide-81
SLIDE 81

October 2007

  • Dr. Bruce Archambeault

81

Charge Depletion for Capacitor @ 400 mils for Various Connection Inductance

slide-82
SLIDE 82

October 2007

  • Dr. Bruce Archambeault

82

Effect of Multiple Capacitors While Keeping Total Capacitance Constant

(power-ground pins at IC center)

12” 10” Port1 (8,7) (Ls 50nH) Port2 (4,5) (power pin)

εr =4.5

Decap Ground pin

1 inch

The decap locations are 800mils, 1200mils, 2700mils from the power pin

  • C=1uF
  • ESL=0.5nH
  • ESR=1Ω
slide-83
SLIDE 83

October 2007

  • Dr. Bruce Archambeault

83

Effect of Multiple Capacitors While Keeping Total Capacitance Constant

(power-ground pins at IC center)

12” 10” Port1 (8,7) (Ls 50nH) Port2 (4,5) (power pin)

εr =4.5

Decap Ground pin

1 inch

The decap locations are 800mils, 1200mils, 2700mils from the power pin

  • C=0.5uF
  • ESL=0.5nH
  • ESR=1Ω
slide-84
SLIDE 84

October 2007

  • Dr. Bruce Archambeault

84

Effect of Multiple Capacitors While Keeping Total Capacitance Constant

(power-ground pins at IC center)

12” 10” Port1 (8,7) (Ls 50nH) Port2 (4,5) (power pin)

εr =4.5

Decap Ground pin

1 inch

The decap locations are 800mils, 1200mils, 2700mils from the power pin

  • C=0.25uF
  • ESL=0.5nH
  • ESR=1Ω
slide-85
SLIDE 85

October 2007

  • Dr. Bruce Archambeault

85

Constant Capacitance 800 mil Distance

slide-86
SLIDE 86

October 2007

  • Dr. Bruce Archambeault

86

Constant Capacitance 800 mil Distance

slide-87
SLIDE 87

October 2007

  • Dr. Bruce Archambeault

87

Constant Capacitance 1200 mil Distance

slide-88
SLIDE 88

October 2007

  • Dr. Bruce Archambeault

88

Constant Capacitance 1200 mil Distance

slide-89
SLIDE 89

October 2007

  • Dr. Bruce Archambeault

89

Constant Capacitance 2700 mil Distance

slide-90
SLIDE 90

October 2007

  • Dr. Bruce Archambeault

90

Constant Capacitance 2700 mil Distance

slide-91
SLIDE 91

October 2007

  • Dr. Bruce Archambeault

91

Example #1 Low Cap Connection Inductance

IC

GND PWR

Cap PCB

slide-92
SLIDE 92

October 2007

  • Dr. Bruce Archambeault

92

Example #2 High Cap Connection Inductance

IC

GND PWR

Cap PCB

slide-93
SLIDE 93

October 2007

  • Dr. Bruce Archambeault

93

Example #1 Hi Cap Connection Inductance

IC

GND PWR

Cap PCB

slide-94
SLIDE 94

October 2007

  • Dr. Bruce Archambeault

94

Example #1 Lower Cap Connection Inductance

IC

GND PWR

Cap PCB

slide-95
SLIDE 95

October 2007

  • Dr. Bruce Archambeault

95

Do’s Don’ts

Mutual Inductance Helps Reduce Path Inductance

  • J. L Knighten, B. Archambeault, J. Fan, et. al., “PDN Design Strategies: II. Ceramic SMT

Decoupling Capacitors – Does Location Matter?,” IEEE EMC Society Newsletter, Issue No. 207, Winter 2006, pp. 56-67.

slide-96
SLIDE 96

October 2007

  • Dr. Bruce Archambeault

96

Effect of Capacitor Value??

  • Need enough charge to supply need
  • Depends on connection inductance

Charge = C*V

slide-97
SLIDE 97

October 2007

  • Dr. Bruce Archambeault

97 Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp) Single Capacitor (with No L) with Various Capacitor Values

  • 0.4
  • 0.3
  • 0.2
  • 0.1

0.1 0.2 0.3 0.4 0.5 0.6 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Level (volts) 750ps Rise, 10 mil planes, (0.0 nH) 1uF @ 400mils 750ps Rise, 10 mil planes,0.01uF @ 400mils 750ps Rise, 10 mil planes, 100pF @ 400mils

slide-98
SLIDE 98

October 2007

  • Dr. Bruce Archambeault

98 Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp) Single Capacitor (with 0.5 nH Connection L) with Various Capacitor Values

  • 0.4
  • 0.3
  • 0.2
  • 0.1

0.1 0.2 0.3 0.4 0.5 0.6 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Level (volts) 750ps Rise, 10 mil planes, (0.5nH) 1uF @ 400mils 750ps Rise, 10 mil planes, (0.5nH) 0.01 uF @ 400mils 750ps Rise, 10 mil planes, (0.5nH) 100 pF @ 400mils

slide-99
SLIDE 99

October 2007

  • Dr. Bruce Archambeault

99 Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp) Single Capacitor (with 1 nH Connection L) with Various Capacitor Values

  • 0.4
  • 0.3
  • 0.2
  • 0.1

0.1 0.2 0.3 0.4 0.5 0.6 0.5 1 1.5 2 2.5 3 3.5 4 Time (ns) Level (volts) 750ps Rise, 10 mil planes, (1nH) 1uF @ 400mils 750ps Rise, 10 mil planes, (1nH) 0.01uF @ 400mils 750ps Rise, 10 mil planes, (1nH) 1000pF @ 400mils 750ps Rise, 10 mil planes, (1nH) 100pF @ 400mils

slide-100
SLIDE 100

October 2007

  • Dr. Bruce Archambeault

100

Noise Voltage is INDEPENDENT of Amount of Capacitance!

As long as there is ‘enough’ charge

Dist=400 mils ESR=30mOhms ESL=0.5nH

slide-101
SLIDE 101

October 2007

  • Dr. Bruce Archambeault

101

Decoupling Summary (1)

  • EMC Frequency Domain analysis

– Steady-state conditions resonances – Transfer function across the board – Measurements and simulations agree well – Distance of capacitors from ASIC load does not change steady-state impedance

slide-102
SLIDE 102

October 2007

  • Dr. Bruce Archambeault

102

Decoupling Summary (2)

  • Charge Delivery Time-Limited analysis

– Using equivalent SPICE circuit from simulations – Current from capacitors change significantly as capacitor moves further away from ASIC – Noise at ASIC pins increase significantly as capacitor moves further away from ASIC – Steady-state frequency domain analysis not sufficient for charge delivery design of decoupling

capacitors

slide-103
SLIDE 103

October 2007

  • Dr. Bruce Archambeault

103

Decoupling Summary (3)

  • Recharge the planes

–Location of Capacitor does matter!

  • Effect more significant for thick dielectrics

–Connection Inductance is important –Value of capacitance not important –More capacitors is better than larger/fewer capacitors

slide-104
SLIDE 104

October 2007

  • Dr. Bruce Archambeault

104

IEEE IEEE