EEC 181 Design Plan By: Christopher Bacchi, Andrea Lopez, Krysteen - - PowerPoint PPT Presentation

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Dec 04, 2023 805 likes •899 views

EEC 181 Design Plan By: Christopher Bacchi, Andrea Lopez, Krysteen Terlouw Algorithm Flowchart Software Profiling Runtime Stage Runtime (%) 1 84 2 12 3 4 Within Stage 1, the inner loop takes 90% of the runtime. Hardware RTL Block

SLIDE 1

EEC 181 Design Plan

By: Christopher Bacchi, Andrea Lopez, Krysteen Terlouw

SLIDE 2

Algorithm Flowchart

SLIDE 3

Software Profiling Runtime

Within Stage 1, the inner loop takes 90% of the runtime.

Stage Runtime (%) 1 84 2 12 3 4

SLIDE 4

Hardware RTL Block Diagram

SLIDE 5

Task Implementations

Software Interface Hardware

Data Compression
Sigoid function
PIOs
FPGA SDRAM
FPGA On CHip
Node Matrix Multiplication
Summing computation
Maximum/final answer

computation

SLIDE 6

Memory Resources & Usage

Weights and Bias Data Compression Image Data Computational Results

Stage 1 & 2 Weight Reduction:

291kB + 48 kB (5x less)

Stage 1&2 Bias Reduction:

2kB → 1kB

SoftMaxTheta:

4kB

Resources Needed:

344kB

FPGA On Chip memory:

625 kB

Test Data Reduction:

7.9MB → 826 kB (10x less)

Resources Needed:

826 kB

HPS SDRAM:

64MB

After data is processed, it will

not move or be rewritten during the entire algorithm.

FPGA On Chip

memory remaining: 281 kB

Immediate

computations and results stored in FPGA On chip memory

SLIDE 7

Performance Prediction

COMPONENT TIME HPS CUSTOM COMPONENT ONCHIP MEMORY SDRAM Process & write X X X Readin NN data X X X start loop thru & wb X X progess sigoid & loop to next stage X X finish all stages & loop to next image X X