EE182 Computer Organization and Design Winter 1998 Chapter 5 - PDF document

EE182 Computer Organization and Design Winter 1998 Chapter 5 Lectures Processor Datapath and Control Part II: Multiple-Cycle Implementation Lecture Handout 5-2: Multiple-Cycle Implementation Slide 1 EE 182 -- Winter 1989 Outline of Part II Lectures Multiple-cycle design The integrated datapath — Finite State Machine control — Advantages and disadvantages — Microprogramming simplifying control implementation — Lecture Handout 5-2: Multiple-Cycle Implementation Slide 2 EE 182 -- Winter 1989

Multi-Cycle Implementation Single-cycle implementation has poor performance Cycle time longer than necessary for all but the slowest instruction — Solution: Break the instruction into smaller steps Execute each step in one clock cycle — • Cycle time: time it takes to execute the longest step • Design all the steps to have similar length • Allow different number of cycles for various instructions Advantages of the multiple cycle processor Cycle time is much shorter — Simple instructions have shorter execution times — • since they can be executed in fewer cycles Functional units can be used more than once/instruction — • so less hardware is required Disadvantages of the multiple cycle processor More timing paths to analyze and tune — Additional registers to store intermediate data values — Lecture Handout 5-2: Multiple-Cycle Implementation Slide 3 EE 182 -- Winter 1989 Multi-Cycle Implementation: Concept Divide data path into multiple steps of 1 clock cycle each instructions execute only necessary steps — • taking 3 to 5 cycles each IF RF EX MEM. WB Instruction Register Execution Memory Write Fetch Fetch back R R P Instr. ALU Data e e C Memory Memory g g s s Lecture Handout 5-2: Multiple-Cycle Implementation Slide 4 EE 182 -- Winter 1989

Overall Approach Timing Methodology Still using an edge-triggered timing methodology, but — • instructions take multiple clocks • functional units (FUs) may be used on different clocks Data used in a clock period must be stable, either — • driven from a register written on earlier clock (a “registered” value) • driven via combinational logic with registered inputs — example: if ALU inputs are stable then the ALU output need not be latched, since it depends combinationally on the stable inputs Our control signals on a given clock cycle will not be determined solely by the decoded instruction A finite state machine is used for sequencing through steps of — instruction execution Key differences from Single-Cycle Implementation: Datapath includes latches for intermediate values and Control includes state for sequencing instruction execution Lecture Handout 5-2: Multiple-Cycle Implementation Slide 5 EE 182 -- Winter 1989 Review of Finite State Machines Finite state machine a set of states and — next state function (determined by current state and input) — output function (determined by current state and input) — We’ll use a Moore machine output based only on current state — — — — — Next state Next-state — Current state function — Clock Inputs Output Outputs function Figure B.27 from text. Lecture Handout 5-2: Multiple-Cycle Implementation Slide 6 EE 182 -- Winter 1989

High-Level View of Multi-Cycle Datapath Instruction register Data PC Address A Register # Instruction Memory Registers ALU ALUOut or data Register # Memory data B Data register Register # Figure 5.30 from text. Single Memory Unit for Instructions and Data With registers to store output during instruction execution — Single ALU for calculating arithmetic/logical results, data memory — addresses, next instruction address Lecture Handout 5-2: Multiple-Cycle Implementation Slide 7 EE 182 -- Winter 1989 Plan: Derive Datapath & Control Start with the basic datapath Look at each instruction class break instruction execution into steps — • each step is one clock cycle • data comes from a “register” and is stored into a “register” in one clock add multiplexors as needed (along with control) — determine how to control the datapath for each step — For each instruction type and each step create a new state — specify the control for that state — determine the next state — Lecture Handout 5-2: Multiple-Cycle Implementation Slide 8 EE 182 -- Winter 1989

Step 1: Instruction Fetch RTL Description IR = Memory[PC]; Path added to PC = PC + 4; figure from text. PC 0 0 Instruction Read M M Address [25–21] register 1 u u x Read x A Instruction Read Zero 1 Memory data 1 1 [20–16] register 2 ALU 0 ALU ALUOut MemData Registers result Instruction Write M Read [15–0] register B u 0 Instruction data 2 Write [15–11] x Instruction 1 M 4 Write data 1 u register data 2 x Instruction 0 3 [15–0] M u x Memory 1 data 16 32 Shift Sign register left 2 extend Lecture Handout 5-2: Multiple-Cycle Implementation Slide 9 EE 182 -- Winter 1989 Step 2: Instruction Decode and Register Fetch RTL Description A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(IR[15-0]) << 2); Note: No control lines depend on the instruction type because the instruction is still being decoded in this step. ALU used to calculate the branch destination just in case we decode a branch instruction. PC 0 0 Instruction Read M M [25–21] register 1 u Address u x Read x A Instruction Read Zero 1 Memory data 1 1 [20–16] register 2 ALU 0 ALU ALUOut MemData Registers result Instruction Write M Read [15–0] register B u 0 Instruction data 2 Write x [15–11] 1 M Instruction 4 Write data 1 u register data 2 x Instruction 0 3 [15–0] M u x Memory 1 16 32 data Shift Sign register left 2 extend Lecture Handout 5-2: Multiple-Cycle Implementation Slide 10 EE 182 -- Winter 1989

Step 3: Execution ALU is performing one of three functions, depending on instruction type RTL Description R-type: ALUOut = A op B; Memory Reference : ALUOut = A + sign-extend(IR[15-0]); Branch: if (A==B) PC = ALUOut; Lecture Handout 5-2: Multiple-Cycle Implementation Slide 11 EE 182 -- Winter 1989 Step 3: R-Type Execution RTL Description R-type: ALUOut = A op B; PC 0 0 Instruction Read M M Address [25–21] register 1 u u x x Read A Instruction Read 1 Memory Zero data 1 1 [20–16] register 2 ALU ALU ALUOut MemData 0 Registers Instruction Write result M Read [15–0] register B u 0 Instruction data 2 Write [15–11] x Instruction 1 M 4 Write data 1 u register data 2 x Instruction 0 3 [15–0] M u x Memory 1 16 32 data Shift Sign register left 2 extend Lecture Handout 5-2: Multiple-Cycle Implementation Slide 12 EE 182 -- Winter 1989

Step 4: R-Type RTL Description R-Type: Reg[IR[15-11]] = ALUOut; This is the last step for R-Type PC 0 0 Instruction Read M M Address [25–21] register 1 u u x x Read A Instruction Read 1 Memory Zero data 1 1 [20–16] register 2 ALU ALU ALUOut MemData 0 Registers Instruction Write result M Read [15–0] register B u 0 Instruction data 2 Write [15–11] x Instruction 1 M 4 Write data 1 u register data 2 x Instruction 0 3 [15–0] M u x Memory 1 16 32 data Shift Sign register left 2 extend Lecture Handout 5-2: Multiple-Cycle Implementation Slide 13 EE 182 -- Winter 1989 Step 3: Load/Store Execution RTL Description Memory Reference : ALUOut = A + sign-extend(IR[15-0]); PC 0 0 Instruction Read M M Address [25–21] register 1 u u x x Read A Instruction Read 1 Memory Zero data 1 1 [20–16] register 2 ALU ALU ALUOut MemData 0 Registers Instruction Write result M Read [15–0] register B u 0 Instruction data 2 Write [15–11] x Instruction 1 M 4 Write data 1 u register data 2 x Instruction 0 3 [15–0] M u x Memory 1 16 32 data Shift Sign register left 2 extend Lecture Handout 5-2: Multiple-Cycle Implementation Slide 14 EE 182 -- Winter 1989

Step 4: Memory RTL Description R-Type: Reg[IR[15-11]] = ALUOut; Load : MDR = Memory[ALUOut]; Store: Memory[ALUOut] = B; Lecture Handout 5-2: Multiple-Cycle Implementation Slide 15 EE 182 -- Winter 1989 Step 4: Load Memory RTL Description Load : MDR = Memory[ALUOut]; PC 0 0 Instruction Read M M Address [25–21] register 1 u u x x Read A Instruction Read 1 Memory Zero data 1 1 [20–16] register 2 ALU ALU ALUOut MemData 0 Registers Instruction Write result M Read [15–0] register B u 0 Instruction data 2 Write [15–11] x Instruction 1 M 4 Write data 1 u register data 2 x Instruction 0 3 [15–0] M u x Memory 1 16 32 data Shift Sign register left 2 extend Lecture Handout 5-2: Multiple-Cycle Implementation Slide 16 EE 182 -- Winter 1989