EE 457 Unit 7d Virtual Memory 2 Virtual Memory Concept A - - PowerPoint PPT Presentation
1 EE 457 Unit 7d Virtual Memory 2 Virtual Memory Concept A mechanism for hiding the details of how much physical memory exists and how its being shared Allows the OS to Efficiently share the physical memory between several
1
2
– Efficiently share the physical memory between several running programs/processes and provide protection against each other – Remove the need of the programmer to know how much memory is physically present and/or give the illusion of more or less physical memory than is present
3
Disk / Secondary Storage ~1-10 ms Main Memory ~ 100 ns L2 Cache ~ 10ns L1 Cache ~ 1ns Registers L1/L2 is a “cache” for main memory Virtual memory provides each process its own address space in secondary storage and uses main memory as a cache
4
– We will focus on HW support for VM
– Double sided surfaces/platters (with R/W head) – Each platter is divided into concentric tracks of small sectors that each store several thousand bits
Surfaces
Read/Write Head 0 Read/Write Head 7 Read/Write Head 1 … Track 0 Track 1 Sector 0 Sector 1 Sector 2
position the read-head above the proper track
to bring the right sector under the read-head
speed (e.g. 5400 RPM)
3-12 ms 5-6 ms 0.1 ms + 2.0 ms ~20 ms
5
to the actual system address range (based on the width of the address bus) of the processor and how much main memory is physically present
private "virtual" address space
– Virtual address space can be larger (or smaller) than physical memory – Virtual address spaces are protected from each other
32-bit Physical Address Space w/
0x00000000 0xffff ffff
Mem. I/O Not used
0x3fffffff
Not used
0x80000000 0xbfffffff
Code
0x00000000 0xffff ffff
32-bit Fictitious Virtual Address Spaces ( > 1GB Mem)
Mapped I/O
1,2,3,…
0x10000000
6
– (def 1.) Address Space + Threads
– (def 2.) : Running instance of a program that has limited rights
access to any other processes' memory
kernel mode) which generally means direct I/O access is disallowed instead requiring system calls into the kernel
– Has access to all resources and much of its code is invoked under the execution of a user process thread
Code
0x00000000 0xffff ffff
Address Spaces
Mapped I/O
1,2,3,…
0x10000000 = Thread
7
1 2 3 Unalloc 1 2 Unalloc
Secondary Storage
… Unalloc … 1 2 3 1 2
Used/Unused Blocks in Virtual Address Space
Code
0x00000000 0xffff ffff
Mapped I/O
1,2,3,…
0x10000000
0 - Code 1 - Code 2 - Data 4 - Heap … 3 - Stack 0 - Code 1 - Code 2 - Data 4 - Heap 3 - Stack
8
1 2 3 Unalloc 1 2 Unalloc … Unalloc … 1 2 3 1 2 0 - Code 1 - Code 2 - Data 4 - Heap … 3 - Stack 0 - Code 1 - Code 2 - Data 4 - Heap 3 - Stack
page-size blocks called "frames"
and their pages can share the physical memory
for pages with secondary storage acting as the backing store (next lower level in the hierarchy)
– Unallocated (not needed yet…stack/heap) – Allocated and residing in secondary storage (Uncached) – Allocated and residing in main memory (Cached)
0x00000000 0x3fffffff
1GB Physical Memory and 32-bit Address Space
0xffffffff
Secondary Storage Fictitious Virtual Address Spaces
frame
0-Code
2-Data
frame I/O and un- used area
9
size "pages" (often around 4KB)
frames (which can hold any page of virtual memory and then be swapped for another page)
while physical layout is not
Physical Frame of memory can hold data from any virtual page. Since all pages are the same size any page can go in any frame (and be swapped at our desire).
0x00000000 0x3fffffff
frame
0-Code
2-Data
frame I/O and un- used area
0xffffffff
unused …
unused unused …
Space
10
addresses
addresses used by the program to the physical address where that page resides
that is not in physical memory, HW generates a "page fault exception" and the OS is invoked to bring in the page to physical memory (possibly evicting another page)
– Each program/process has VA: 0x00000000
Translation Unit / MMU (Mem. Mgmt. Unit)
Proc. Core
Memory
Data PA: 0x0 PA:0x3fffffff
frame
0-Code
Physical Memory and Address Space
2-Data
frame I/O and un- used area
0xffffffff
Secondary Storage Fictitious Virtual Address Spaces
1 2 3 Unalloc 1 2 Unalloc … Unalloc … 1 2 3 1 2 0 - Code 1 - Code 2 - Data 4 - Heap … 3 - Stack 0 - Code 1 - Code 2 - Data 4 - Heap 3 - Stack
PA: 0x11f000 PA: 0x21b000 VA: 0x040000 VA: 0x100080 Virtual Addr Physical Addr VA: 0x040000 PA: 0x21b000
11
memory and uses virtual addresses and necessary data is broken into large chunks called pages
main memory acting as a cache and allowing sharing
translation between:
– Virtual address: Address used by the process (programmer) – Physical address: Physical memory location of the desired data
programs
Translation Unit / MMU (Mem. Mgmt. Unit)
Proc. Core
Virtual Addr
Memory
Physical Addr Data PA: 0x0 PA:0x3fffffff
frame
0-Code
Physical Memory and Address Space
2-Data
frame I/O and un- used area
0xffffffff
Secondary Storage Fictitious Virtual Address Spaces
1 2 3 Unalloc 1 2 Unalloc … Unalloc … 1 2 3 1 2 0 - Code 1 - Code 2 - Data 4 - Heap … 3 - Stack 0 - Code 1 - Code 2 - Data 4 - Heap 3 - Stack
PA: 0x11f000 PA: 0x21b000 VA: 0x040000 VA: 0x100080
12
– Implies page size should be fairly large (i.e. once we’ve taken the time to find data on disk, make it worthwhile by accessing a reasonably large amount of data) – Implies the placement of pages in main memory should be fully associative to reduce conflicts and maximize page hit rates – Implies a "page fault" is going to take so much time to even access the data that we can handle them in software (via an exception) rather than using HW like typical cache misses – Implies eviction algorithms like LRU can be used since reducing page miss rates will pay off greatly – Implies write-back (write-through would be too expensive)
13
Page Tables
14
(several KB) to amortize the large access time
unit = MMU (Mem. Management Unit)
up translations from VPN to PPFN
Offset within page
Virtual Address
Virtual Page Number
31 12 11
Offset within page
Physical Address
Number
31 30 12 11
00
Copied
12
Translation Process (MMU + Page Table)
29 20 18
2 2 1 b
Lookup VPN 0x00040 to it lives in PPFN: 0x0021b
15
should be fully associative
– For 1GB of physical memory, a 4KB page can be anywhere in the 256K = 218 page frames
techniques to cache
– TAG = VPN that is currently stored in the frame
– TAG = 20 + 1 = 21 bits, 218 comparators…TOO MUCH
PAGE TABLE
Frame 2 Frame 1 Frame 0 … Frame 218-1 VPN
Page Frame # Virtual Address
= = = = = Physical Memory Processor
Tag (VPN) V M Tag (VPN) V M Tag (VPN) V M … Tag (VPN) V M 218-1 2 1
16
– Let us assume 1000 contacts represented by a 3-digit integer (0-999) in the cell phone (this ID can be used to look up their names) – We want to use a simple array (or Look-Up Table (LUT)) to translate phone numbers to contact ID’s, how shall we organize/index our LUT
213-745-9823
LUT indexed w/ contact ID
000
LUT indexed w/ all possible phone #’s
626-454-9985 … 323-823-7104 818-329-1980 001 002 999 null 000-000-0000 .. … null 000 213-745-9823 999-999-9999
Sorted LUT indexed w/ used phone #’s
436 213-745-9823 000 … 002 999 323-823-7104 213-730-2198 818-329-1980
O(n) - Doesn’t Work We are given phone # and need to translate to ID (1000 accesses) O(log n) - Could Work Since its in sorted order we could use a binary search (log21000 accesses) O(1) - Could Work Easy to index & find but LARGE (1 access) 1 2 3
…
17
– VPN (upper bits) + Page offset: Based on page size (i.e. 0 to 4K-1 for 4KB page)
(i.e. like an array access where VPN is the index: PTBR[VPN] )
– Each entry is referred to as a Page Table Entry (PTE) and holds the physical frame number & bookkeeping info
VA
Offset w/in page Virtual Page Number
31 12 11
Page Table Size = 220 entries * 18 bits = approx. 220*4bytes = 4MB
PTBR = Page Table Base Reg. Offset w/in page
PA
31 12 11
00
PTE Page Frame Number PTE …
Other flags 20
Page Table in Main Memory
18
Processor
0xc0008000 0xc0008000 PTBR[2] PTBR[1] PTBR[0] … 0x0021b 0x0021b 0x00002 0x2d8 0x2d8
18
VPN P1-VAS 1 2 3 4 5 6 7
Page Table VA
Offset VPN
7
Offset
PA
PFN
4 4 9
Page Table
0x00 0x1F 0x20 0x3F 0x40 0x5F 0xE0 0xFF
PFN
Phys Mem
VP 3 1 2 VP 1 3
PT for P1 (OS Owns)
31 VP 5
0x000 0x01F 0x020 0x03F 0x040 0x05F 0x3E0 0x3FF
V Entry 0x1a 1 1 0x02 2 1 0x18 3 1 0x00 4 0x10 5 1 0x1F 6 0x15 7 0x0A
19
V Entry 0x0E 1 1 0x1E 2 1 0x16 3 1 0x06 4 0x0B 5 1 0x1F 6 0x15 7 0x0A
Page Table
VA PA 0x2D = 0010 1101 0x3CD 0x7A = 0111 1010 0x0DA 0xEF = 1110 1111 INVALID 0xA8 = 1010 1000 0x3E8
VA
Offset VPN
7
Offset
PA
PFN
4 4 9
Page Table
20
requires 1 access) but somehow reduce the size especially since much of it is unused?
area codes.
– 1st level LUT is indexed on area code and contains pointers to 2nd level tables – 2nd level LUT’s indexed on local phone numbers and contains contact ID entries LUT indexed w/ all possible phone #’s
null … … 000 213 323
1st Level Index = Area Code
Area Code null 000-000-0000 .. … null 000 213-745-9823 999-999-9999 … 213 Table
2nd Level Index = Local Phone #
000-0000 999-9999 323 Table 000-0000 999-9999
If only 2 used area codes then only 1000 + 2(107) entries rather than 1010 entries
21
– 1st Level = Area code and pointers to 2nd level tables – 2nd Level = First 3-digits of local phone and pointers to 3rd level tables – 3rd Level = Contact ID’s
null … … 000 213 323
1st Level Index = Area Code
Area Code …
2nd Level Index = Local Phone #
000 999 000 999 323 Table 213 Table null null 745 823 null null
3rd Level Index = Local Phone #
000 999 213-745 Table null 000 null 9823 000 999 323-823 Table null 999 null 7104
22
third level table for just this entry
null … … 000 213 323
1st Level Index = Area Code
Area Code …
2nd Level Index = Local Phone #
000 999 000 999 323 Table 213 Table null null 745 823 null null
3rd Level Index = Local Phone #
000 999 213-745 Table null 000 null 9823 000 999 323-823 Table null 999 null 7104
23
– Internal nodes contain pointers to other page tables – Leaves hold actual translations
0x40 0x040 0x35 Virtual Addr VPN
Idx1 Idx2 7 bits 7 bits 12 bits 0xd0000 PDBR/CR3 … … 0x3f 6 bits Idx3 [0x40] PT2[] = start addr PD start addr [0x3f] [0x35] PT3[] = start addr Level 1 Level 2 Level 3
Translations live in this level
Processor
level mean no table at the next (saving space)
Page Directory
24
Uncached Page Uncached Page Uncached Page Uncached Page Uncached Page Uncached Page
1 2 1023 1 2 1023 1 2 1023 1 2 1023
Offset w/in page Level Index 1
31 12 11 22 21
Level Index 2
10 10
Pointer to start of 2nd Level Table PPFN’s
frame I/O and un- used area frame
0x0
When HW encounters a PTE whose page is not in physical memory, it will generate a page fault exception and the OS will take over and retrieve the page before resuming the program.
25
Offset w/in page
Index 1
8 11 6
Index 2 Process ID Index 3
6
4095 MMU hold 4096 entry table (one entry per context/process) [Essentially, PTBR for each process] Context Table First Level Second Level Third Level 4K Page Desired word PPFN 28 * 4 bytes 26 * 4 bytes 26 * 4 bytes
How many accesses to memory does it take to get the desired word that corresponds to the given virtual address? Would that change for a 1- or 2- level table?
Virtual Address:
26
Page Frame Number Valid / Present Modified / Dirty Referenced Protection Cacheable
27
28
keeping statistics to implement LRU
some kind of timestamp). This is too much to do in HW and we don’t want to use SW when we have hits
pseudo-LRU algorithm
– HW will set the “Referenced” bit when a page is used – At certain intervals, SW will use these reference bits to keep statistics on which pages have been used in that interval and then clear the reference bits – On replacement, these statistics can be used to find the pseudo-LRU page
29
Cache Virtual Memory Block Size 16-64B 4 KB – 64 MB Mapping Schemes Direct or Set Associative Fully Associative Miss handling and replacement HW SW Replacement Policy Full LRU if low associativity / Random is also used Pseudo-LRU can be implemented
30
– Without VM, only requires 10ns cache access time – With VM, address must first be translated via the page table (recall page table is in memory)
31
Translation Unit / MMU
associativity (at least 4-way and many times fully associative) to avoid conflicts – On hit, the PPFN is produced and concatenated with the offset – On miss, a page table walk is needed
TLB I or D Cache
CPU
VA VPN Page Offset PPFN PA data 10 ns 10 ns
Memory Memory (Page Table)
Hit Miss Miss Hit
Processor
32
Offset w/in page
Virtual Address
Virtual Page Number
31 12 11
Page Frame #
Offset w/in page
Physical Address
31 12 11
V M Tag = VPN
= = = =
TLB Fully Direct Set-Assoc.
20 12
Index
Byte Offset
Data Data Data Data Tag V
= Hit
Desired Data 14 16
TLB Data Cache Fully Direct Set-Assoc. MMU Cache If data cache is tagged with physical addresses, then we must translate the VA before we can access the data cache.
TLB only has a few entries so now we need to store tags.
33
– 1 tag (to identify the block) corresponds to MANY bytes (16-64 bytes)
– 1 tag (VPN) corresponds to 1 translation (PTE/PPFN) which is good for 4KB
TLB
(1 tag = 1 translation. No Offset needed)
Instruc./Data Cache
(Offset needed since one tag corresponds to many values)
34
Tag Block
Word Byte Offset
18 10 2 2
35
– On hit, page frame # supplied quickly w/o page table access
Offset w/in page
Virtual Address
VPN
31 12 11
Offset w/in page
Physical Address
31 12 11
Set Tag
308ac 7ffe Tag PF# Tag PF# Tag PF# Tag PF#
= = = =
Way 1 Way 0 Way 2 Way 3
4 16
7 f f e 1 6 d 8 3 8 a c 6 d 8 7 f f e 1
What is the page size? 4KB Tag size? 16 bits Comparator Width? 5-bits (4+V)
36
Processor Chip Translation Unit / MMU
disk to evict old page (if dirty) and to bring in desired page
– Likely context switch on each access since disk is slow
appropriately
TLB Cache
CPU
VA VPN Page Offset PPFN PA data 10 ns
Miss Miss Hit
VA Miss Invalid / Not Present OS Exception (Page Fault) Handler
Memory
1 2 3 3 4
frame free (update PT & TLB)
and update PT
4 5
Restart faulting instruction
3 4
Page Table
4 3 Disk Driver (Interrupt) 6
TLB Miss / PT walk / Update TLB
6
37
Microprocessor AMD Opteron P4 PPC 7447a Virtual Address 48-bit 32- or 48-bit 52-bit Physical Address 40-bit 36-bit 32- or 36-bit TLB Entries (I/D/L2 TLB) L1: 40/40 L2: 512/512 L1: 128/128 L1: 128 / 128 TLB Mapping L1: Fully L2: 4-way SA Fully (? 4-way) 2-way set associative
4 KB 4 KB 4 KB
Notes: Large VA’s include ASID (process ID’s) and other segment information Sources: H&P, “CO&D”, 3rd ed., Freescale.com,
38
– Variable page size settable by OS to allow for different working set sizes – Example: 64 TLB entries and 4 KB pages = 256KB
39
OS
– MMU can perform the TLB search followed by a page table walk if needed – If page fault occurs, OS takes over to bring in the page
– MMU performs TLB Search – If TLB miss, OS can perform page table walk and bring in page if necessary
– First flush out blocks belong to that page from cache (writing back if necessary) – Invalidate tags of those blocks – Invalidate TLB entry (if any) corresponding to that page
– If page is dirty, copy page back to the disk – Simple way to remember this…
40
– Cache contents are a (subset / superset) of main memory contents – Main memory contents are a (subset / superset) of page/swap file on disk – TLB contents are a (subset / superset) of page table contents
41
TLB VM Cache Possible Y/N & Description Hit Hit Hit Possible: best-case scenario Hit Hit Miss Possible: TLB hits (hit in VM is implied), then cache miss Miss Hit Hit TLB misses, then hits in page table, then cache hit Miss Hit Miss TLB misses, then hits in page table, then cache miss Miss Miss Miss TLB misses, then page fault, then miss in cache Hit Miss Miss Impossible: cannot hit in TLB if page not present Hit Miss Hit Impossible: cannot hit in TLB if page not present Miss Miss Hit Impossible: data cannot be in cache if page not present
Taken from H & P, “Computer Organization” 3rd, Ed.
42
43
– Wait for full address translation – Then use physical address for both indexing and tag comparison
– Use portion of the virtual address for indexing then wait for address translation and use physical address for tag comparisons – Easiest when index portion of virtual address w/in offset (page size) address bits, otherwise aliasing may occur
– Use virtual address for both indexing and tagging…No TLB access unless cache miss – Requires invalidation of cache lines on context switch or use of process ID as part of tags
Offset
VA
VPN
31 12 11
Offset
PA
PFN
31 12 11
Set/Blk Tag
PIPT
Offset
VA
VPN
31 12 11
Offset
PA
PFN
31 12 11
Tag Set/Blk Offset
VA
VPN
31 12 11
Offset
PA
PFN
31 12 11
Set/Blk Tag
VIPT VIVT
44
– Can choose to only hold translations for current process and thus invalidate all entries on context switch – Can hold translations for multiple processes concurrently by concatenating a process or address space ID (PID or ASID) to the VPN tag
Offset
VA
VPN
31 12 11
ASID
Unique ID for each process
Page Frame # V M Tag
= = = =
ASID
45
1 2 3 1 2
… …
1 2
…
Physical Memory Virtual Address Spaces P1 P2
46
D-Cache D-TLB
Cache Data Cache Tag Lookup
Tag Check
Single Memory Stage in 5- Stage Pipeline Expand to three stages when TLB and Cache access is balanced
47
– This is harmless since it’s fine to start the decode and read registers even if it’s an invalid tag so long as we know by the end of the clock
IM
Reg
ALU
DM
Reg
IF IS RF EX DF DS TC WB TLB Data/Tag Access Tag Check TLB Data/Tag Access Tag Check
48
– Possible since data is available at end of DS and can be forwarded – If tag check indicates a miss the pipeline can be “backed up” (re-execute the instruction when the data is available
IM
Reg
ALU
DM
Reg
IM
Reg
ALU
DM
Reg
IM
Reg
ALU
DM
Reg
IM
Reg
ALU
DM
Reg
LW $5,0($2) ADD $1,$1,$5
49
– 64-bit data, 32-bit virtual/physical address – Page Size: 128KB – TLB Size: 256 entry 4-way set associative – Page Table Org.: 3-levels
(2nd level tables) followed by some number of C-Tables (3rd level)
– Cache Organization
50
– 64-bit data, 32-bit virtual/physical address – Cache Organization: Block size: 2 words [1 Word = 64-bits = 8 bytes]
2 Banks so we can quickly get two words to the data cache when a block is transferred
Physical Address
Word 31 Byte
Proc.
Bank 0 (A3=0) Bank 1 (A3=1)
/BE7…/BE0 64 29 A31-A3
Block ID 8 8 31 3 2 1 0 Byte
31
Logical Address Bus Logical Address Bus
3 4 2 1 0
64-bit Data bus = 8 bytes = 8 Byte enables (/BE7…/BE0)
28 28
51
– 64-bit data, 32-bit virtual/physical address – Page Size: 128KB – TLB Size: 256 entry 4-way set associative
Logical Address Bus
Page Size = 128KB => Offset Field Size = 17-bits # of TLB Sets: 256 entries / 4 entries per set = 64 sets => 6 set bits Offset VPN
31 17 16
Tag Set
17 23 31 22
52
– Page Size: 128KB – Page Table Org.: 3-levels
32 entry B-Tables (2nd level tables) some number of C-Tables (3rd level)
Virtual Address
VPN = 15-bits Level 1 Page Table = 64 (26) entries => 6-bits Level 2 Page Table = 32 (25) entries => 5-bits Level 3 Page Table = 15-6-5= 4-bits => 16 (24) entries Offset=17-bits VPN=15-bits
31 17 16 Level 1 4 5 6 Level 2 Level 3
53
– Cache Organization
64-bit data = 8 (23) bytes per word Block Size = 2 (21) words = 1 word bit # of Cache blocks = 512KB / 16 bytes per block = 219 / 24 = 215 # of Sets = 215 / 23 ways per set = 212 sets => 12 set bits # of Tag bits = 32 – 12 – 1 – 3 bits = 16-bits
Logical Address Bus
Word
3 Tag Set 1 16
31
12
Byte
54
8 comparators of 17-bits Tag RAM Size = 4K x 17
Logical Address Bus
Word
3 Tag Set 1 16
31
12
Byte
Set Tag RAM DI[16:0]
DO[16:0]
A15-A4 A31-A16 + V-bit A[11:0]
=
Hit/Miss Tag
12 17 17