Credits These slides were derived from Gandhi Puvvadas EE 457 Class - PowerPoint PPT Presentation

1.1 1.2 Credits • These slides were derived from Gandhi Puvvada’s EE 457 Class Notes EE 457 Unit 1 Overview of Digital System Design 1.3 1.4 Typical Logic Gate • Gates can output two values: 0 & 1 Hot Water = Logic 1 – Logic ‘1’ (Vdd = 3V), or Logic ‘0’ (Vss = GND) Cold Water = Logic 0 • Analogy: a sink faucet – 2 possibilities: Hot (‘1’) or Cold (‘0’) • Inputs cause EITHER a pathway from output to VDD OR VSS +3V +3V Inputs Vdd PMOS PMOS TRI-STATE OUTPUTS & BUSES Inputs Inputs Output Output NMOS NMOS Vss

1.5 1.6 Output Connections Tri-State Buffers +3V • Can we connect the output of two logic gates together? • Gates can output two values: 0 & 1 1. Logic 0 = 0 volts PMOS 2. Logic 1 = 5 volts Inputs Output • Tristate buffers can output a third value: Inputs Vdd NMOS 3. ____ = ___________________ Src 1 (no connection to any voltage source) Src 1 • Analogy: a sink faucet – 3 possibilities: Vss Src 2 1.) Hot water, Inputs Vdd 2.) Cold water, 3.) _____________ Hot Water = Logic 1 Src 2 Src 3 Cold Water = Logic 0 Vss 1.7 1.8 Tri-State Buffers Tri-State Buffers • We use tri-state buffers to share one output • Tri-state buffers have Tri-State Buffer amongst several sources an extra enable input In Out • Rule: ______________________________ • When disabled, output E is Z Src 1 Enable E • When enabled, normal EN1 buffer En In Out Src 2 D Q 0 x Z E D-FF 1 0 0 EN2 Q CLK 1 1 1 Src 3 E EN3

1.9 1.10 Tri-State Buffers Communication Connections • We use tri-state buffers to share one output amongst several • Multiple entities need to communicate sources • When 1 buffer enabled, its output overpowers the Z’s (no • We could use connection) from the other gates – Point-to-point connections – A _______________________ 0 0 output of 0 E Select source Separate point to point overpowers 1 to pass its 1 connections the Z data ______________________ 0 1 Z D Q E D-FF 0 Q CLK 0 Z Disabled E buffers 0 output ‘Z’ 1.11 1.12 Bidirectional Bus Tri-State Buffer / Bussing Summary • Provide a 3 rd output value: ________________ • ___ transmitter (otherwise bus contention) • Allows multiple outputs to be wired together • N receivers • Only _____ bus driver can be enabled at a time 0 1 0 0

1.13 1.14 Digital Design Goals • Digital systems seek to optimize a design along these three axes: Area – Area (size) Power – Speed – Power Consumption Speed • Can often only optimize one or two of these without sacrificing the other(s) MICROARCHITECTURE EXAMPLE – Just as in software design, there is a classic time/space trade-off – Microarchitecture can determine where a design falls in this trade space 1.15 1.16 Different Architectures Single Bus Two-Bus Three Bus R0 R0 R0 R1 R1 R1 Rn Rn Rn Y Reg. Y Reg. Y Reg. Clocking Strategies ALU ALU ALU REGISTERS & DATA ENABLES Z Reg. Z Reg. Z Reg. Clock 1: Y = Rsrc1 Clock 1: Z = Rsrc1 + Rsrc2 Clock 1: Rdst = Rsrc1 + Rsrc2 Clock 2: Z = Rsrc2 + Y Clock 2: Rdst = Z Clock 3: Rdst = Z General Implications: Less Resources => More Clock Cycles (Time)

1.17 1.18 Registers Example: Accumulator D0 D Q Q0 • A Register is a group of D-FF’s • Sum a time-based sequence of numbers CLR tied to a common clock and • A register usually stores a single logic value (i.e. a number) clear (reset) input D1 Q1 D Q – Clear can be asynchronous or CLR time synchronous 9, 3, 2 • Used to store multiple bit Clock D2 D Q Q2 Y0 Z0 values on each clock cycle X0 A0 S0 D Q CLR Reset X1 A1 CLR X2 A2 Y1 Z1 S1 D Q X3 A3 2 3 9 X 4-bit CLR Adder Y2 Z2 D3 D Q Q3 CLK RST D i Q i * B0 S2 D Q B1 CLR CLR 2 5 14 Y 1,0 X X Q i B2 Y3 Z3 S3 D Q B3 ↑ 1 X 0 CLR RST Z 0 2 5 14 Clock Reset ↑ 0 0 0 CLK Register ↑ 0 1 1 4-bit Register 1.19 1.20 Synchronous vs. Asynchronous Registers • The set/preset and clear inputs can be built to be synchronous • Whatever the D value is at the clock edge is sampled or asynchronous and passed to the Q output until the next clock edge • These terms refer to when the initialization takes place – Asynchronous Reset (AR): Initialization of Q takes effect immediately regardless of the CLK – Synchronous Reset (SR): Initialization of Q takes effect only at an edge (clear must be active at the edge) Synchronous Asynchronous CLK Clock Clock RST CLR CLR D[3:0] 0010 0011 0100 0101 0110 0111 1000 1001 1010 Q ’ s Q ’ s Q[3:0] ? 0000 0011 0100 1001 0101 0110 0111 1000 Synchronous SET or CLR Asynchronous SET or CLR 4-bit Register – On clock edge, D is passed to Q means the signal must be means Q will initialize as soon active at a clock edge before as the SET or CLR signal is Q will initialize activated

1.21 1.22 Clocking Option 1 Selective Loading/Registering of Data • Use Load as the clock signal • What if we only want a register Q0 D0 D Q to capture data on selective CLR • (Does/Doesn’t) Work. D0 D Q Q0 CLR clocks (and not on EVERY clock) • ________________ D1 D Q Q1 – Clocks are indicated with a “LOAD” D1 D Q Q1 CLR signal CLR Desired Load time D2 D Q Q2 D2 D Q Q2 CLR CLR D Q Q3 D3 D3 D Q Q3 CLR CLR RST RST Actual Load LOAD = CLK CLK time Want to load the register on the indicated clock cycles and have it retain its value in the 4-bit Register other cycles 1.23 1.24 Clocking Option 2 Glitches • Use ~Load (inverted Load) as the • Temporary (transient) incorrect / toggling output values D0 D Q Q0 due to differing delay paths of the inputs clock signal CLR – Eventually output settles to correct value • (Does/Doesn’t) Work. – Unless a circuit is specially designed, glitches are possible on all D1 Q1 D Q circuits • ________________ CLR Desired D2 D Q Q2 Load time CLR D3 D Q Q3 CLR RST ~LOAD = CLK Actual Load time

1.25 1.26 Successive Loading Clocks Option 3 D0 Q0 D Q • Gate the clock with the load • If load is held high on two successive clock CLR signal cycles will get _________ edge(s) • Also susceptible to glitches D1 D Q Q1 CLR D2 D Q Q2 CLR D3 D Q Q3 CLR RST CLK 4-bit Register 1.27 1.28 Option 4: Feedback mux Option 4: Feedback mux • Registers (D-FF’s) will sample the D • Registers (D-FF’s) will sample the D 0 bit every clock edge and pass it to Q bit every clock edge and pass it to Q 1 Y D Q Q 0 • Sometimes we may want to hold the • Sometimes we may want to hold the SET D 1 S Q Y D Q CLR value of Q and ignore D even at a D 1 S value of Q and ignore D even at a EN CLR clock edge clock edge CLK EN RST AR CLK • We can add an enable input and • We can add an enable input and /AR some logic in front of the D-FF to some logic in front of the D-FF to FF with Data Enable FF with Data Enable accomplish this accomplish this (Always clocks, but selectively (Always clocks, but selectively chooses old value, Q, or new chooses old value, Q, or new value D) value D) CLK /AR EN D i Q i * CLK AR EN D i Q i * X 0 X X 0 X 1 X X 0 0,1 1 X X Q i 0,1 0 X X Q i ↑ ↑ 1 0 X Q i 0 0 X Q i ↑ ↑ 1 1 0 0 0 1 0 0 ↑ ↑ 1 1 1 1 0 1 1 1

1.29 1.30 Registers w/ Enables Registers w/ Enables Q • The D value is sampled at the clock edge only • When EN=0, Q value is 0 Q D Q Q Y D 1 if the enable is active passed back to the input S CLR 0 EN and thus Q will maintain its CLK • Otherwise the current Q value is maintained RST value at the next clock edge When EN=0, Q is • When EN=1, D value is recycled back to the input passed to the input and CLK thus Q will change at the RST 0 D Q edge based on D Y D Q D D 1 S EN CLR 1 EN CLK D[3:0] 0011 0100 0010 0101 0110 0111 1000 1001 1010 RST Q[3:0] 0000 0101 0111 1000 When EN=1, D input is passed to FF input 1.31 1.32 Counters Register With or Without An Enable Free-Running Register Register with Load (Data) Enable 0 • Increment (Add 1 to Q) at each D0 Q0 Y D Q Q0 D Q D0 1 S CLR CLR clock edge Adder (+) Q Register – Up Counter: Q* = Q + 1 0 1 Q1 D1 D Q Q1 Y D Q D1 1 S • Standard counter components CLR CLR RESET include other features 0 CLK Y D Q Q2 D2 D Q Q2 D2 1 S – Enables: Will not count at edge if CLR CLR EN=0 0 D Q Q3 – Resets: Reset count to 0 D3 D Q Q3 Y 1 D3 S CLR CLR – Parallel Load Inputs: Can initialize EN count to a value P (i.e. Q* = P rather RST RST CLK CLK than Q+1) When to use one vs. the other? • Free-running register: Do you want to update the stored value EVERY edge • Register w/ Enable: In all other cases…