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DRAM 1 Dynamic Random Access Memory (DRAM) Storage Charge on a - PowerPoint PPT Presentation

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DRAM 1 Dynamic Random Access Memory (DRAM) Storage Charge on a capacitor Decays over time (us-scale) This is the dyanamic part. About 6F 2 : 20x better than SRAM Reading Precharge Assert word line

  1. DRAM 1

  2. Dynamic Random Access Memory (DRAM) • Storage • Charge on a capacitor • Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than SRAM • Reading • Precharge • Assert word line • Sense output Only one bit line is read at a time. • Refresh data The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown. 2

  3. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor Wordline 0 • Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than Wordline 1 SRAM • Reading • Precharge • Assert word line + - • Sense output Only one bit line is read at a time. • Refresh data The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown. 2

  4. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor Wordline 0 • Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than Wordline 1 SRAM • Reading • Precharge • Assert word line + - • Sense output Only one bit line is read at a time. • Refresh data The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown. 2

  5. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor Wordline 0 • Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than Wordline 1 SRAM • Reading • Precharge • Assert word line + - • Sense output Only one bit line is read at a time. • Refresh data The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown. 2

  6. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor Wordline 0 • Decays over time (us-scale) Bit destroyed! • This is the “dyanamic” part. • About 6F 2 : 20x better than Wordline 1 SRAM • Reading • Precharge • Assert word line + - • Sense output Only one bit line is read at a time. • Refresh data The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown. 2

  7. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor Wordline 0 • Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than Wordline 1 SRAM • Reading • Precharge • Assert word line + - • Sense output Only one bit line is read at a time. • Refresh data The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown. 2

  8. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor Wordline 0 • Bit Restored Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than Wordline 1 SRAM • Reading • Precharge • Assert word line + - • Sense output Only one bit line is read at a time. • Refresh data The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown. 2

  9. DRAM: Write and Refresh Bitline 0 Bitline 1 • Writing Wordline 0 • Turn on the wordline • Override the sense amp. • Refresh Wordline 1 • Every few milli-seconds, read and re-write every bit. • Consumes power • Takes time + - 3

  10. DRAM Lithography 4

  11. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder 5

  12. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Row Address 5

  13. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Row Address 5

  14. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Row Address 5

  15. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder 5

  16. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  17. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  18. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  19. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  20. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder 5

  21. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  22. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  23. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  24. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder Column Address 5

  25. Accessing DRAM • Apply the row address One DD3 8K bits DRAM bank • “opens a page” Row decoder • Slow (~12ns read + High order bits DRAM array 24 ns precharge) 16k Rows • Contents in a “row buffer” • Apply one or more Sense Amps column addrs • fast (~3ns) Row Buffer • Reads and/or writes Low order bits Column decoder 5

  26. DRAM Devices • There are many banks per die (16 at left) • Multiple pages can be open at once. • Can keep pages open longer • Parallelism • Example • open bank 1, row 4 • open bank 2, row 7 • open bank 3, row 10 • read bank 1, column 8 • read bank 2, column 32 • ... Micron 78nm 1Gb DDR3 6

  27. DRAM: Micron MT47H512M4 7

  28. DRAM: Micron MT47H512M4 8

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