DRAM 1 Dynamic Random Access Memory (DRAM) Storage Charge on a - - PowerPoint PPT Presentation

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DRAM 1 Dynamic Random Access Memory (DRAM) Storage Charge on a - - PowerPoint PPT Presentation

Dec 05, 2022 229 likes •550 views

DRAM 1 Dynamic Random Access Memory (DRAM) Storage Charge on a capacitor Decays over time (us-scale) This is the dyanamic part. About 6F 2 : 20x better than SRAM Reading Precharge Assert word line

slide-1
SLIDE 1

DRAM

1

slide-2
SLIDE 2

Dynamic Random Access Memory (DRAM)

  • Storage
  • Charge on a capacitor
  • Decays over time (us-scale)
  • This is the “dyanamic” part.
  • About 6F2: 20x better than

SRAM

  • Reading
  • Precharge
  • Assert word line
  • Sense output
  • Refresh data

Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

2

slide-3
SLIDE 3

Dynamic Random Access Memory (DRAM)

  • Storage
  • Charge on a capacitor
  • Decays over time (us-scale)
  • This is the “dyanamic” part.
  • About 6F2: 20x better than

SRAM

  • Reading
  • Precharge
  • Assert word line
  • Sense output
  • Refresh data

Wordline 0 Bitline 0 Wordline 1 Bitline 1

  • +

Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

2

slide-4
SLIDE 4

Dynamic Random Access Memory (DRAM)

  • Storage
  • Charge on a capacitor
  • Decays over time (us-scale)
  • This is the “dyanamic” part.
  • About 6F2: 20x better than

SRAM

  • Reading
  • Precharge
  • Assert word line
  • Sense output
  • Refresh data

Wordline 0 Bitline 0 Wordline 1 Bitline 1

  • +

Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

2

slide-5
SLIDE 5

Dynamic Random Access Memory (DRAM)

  • Storage
  • Charge on a capacitor
  • Decays over time (us-scale)
  • This is the “dyanamic” part.
  • About 6F2: 20x better than

SRAM

  • Reading
  • Precharge
  • Assert word line
  • Sense output
  • Refresh data

Wordline 0 Bitline 0 Wordline 1 Bitline 1

  • +

Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

2

slide-6
SLIDE 6

Dynamic Random Access Memory (DRAM)

  • Storage
  • Charge on a capacitor
  • Decays over time (us-scale)
  • This is the “dyanamic” part.
  • About 6F2: 20x better than

SRAM

  • Reading
  • Precharge
  • Assert word line
  • Sense output
  • Refresh data

Wordline 0 Bitline 0 Wordline 1 Bitline 1

  • +

Bit destroyed!

Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

2

slide-7
SLIDE 7

Dynamic Random Access Memory (DRAM)

  • Storage
  • Charge on a capacitor
  • Decays over time (us-scale)
  • This is the “dyanamic” part.
  • About 6F2: 20x better than

SRAM

  • Reading
  • Precharge
  • Assert word line
  • Sense output
  • Refresh data

Wordline 0 Bitline 0 Wordline 1 Bitline 1

  • +

Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

2

slide-8
SLIDE 8

Dynamic Random Access Memory (DRAM)

  • Storage
  • Charge on a capacitor
  • Decays over time (us-scale)
  • This is the “dyanamic” part.
  • About 6F2: 20x better than

SRAM

  • Reading
  • Precharge
  • Assert word line
  • Sense output
  • Refresh data

Wordline 0 Bitline 0 Wordline 1 Bitline 1

  • +

Bit Restored

Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

2

slide-9
SLIDE 9

DRAM: Write and Refresh

  • Writing
  • Turn on the wordline
  • Override the sense amp.
  • Refresh
  • Every few milli-seconds,

read and re-write every bit.

  • Consumes power
  • Takes time

Wordline 0 Bitline 0 Wordline 1 Bitline 1

  • +

3

slide-10
SLIDE 10

DRAM Lithography

4

slide-11
SLIDE 11

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

16k Rows

One DD3 DRAM bank

5

slide-12
SLIDE 12

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Row Address

16k Rows

One DD3 DRAM bank

5

slide-13
SLIDE 13

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Row Address

16k Rows

One DD3 DRAM bank

5

slide-14
SLIDE 14

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Row Address

16k Rows

One DD3 DRAM bank

5

slide-15
SLIDE 15

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

16k Rows

One DD3 DRAM bank

5

slide-16
SLIDE 16

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-17
SLIDE 17

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-18
SLIDE 18

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-19
SLIDE 19

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-20
SLIDE 20

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

16k Rows

One DD3 DRAM bank

5

slide-21
SLIDE 21

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-22
SLIDE 22

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-23
SLIDE 23

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-24
SLIDE 24

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

Column Address

16k Rows

One DD3 DRAM bank

5

slide-25
SLIDE 25

Accessing DRAM

  • Apply the row address
  • “opens a page”
  • Slow (~12ns read +

24 ns precharge)

  • Contents in a “row

buffer”

  • Apply one or more

column addrs

  • fast (~3ns)
  • Reads and/or writes

Row decoder Column decoder Sense Amps High order bits Low order bits

DRAM array

8K bits

Row Buffer

16k Rows

One DD3 DRAM bank

5

slide-26
SLIDE 26

DRAM Devices

  • There are many banks

per die (16 at left)

  • Multiple pages can be open

at once.

  • Can keep pages open

longer

  • Parallelism
  • Example
  • pen bank 1, row 4
  • pen bank 2, row 7
  • pen bank 3, row 10
  • read bank 1, column 8
  • read bank 2, column 32
  • ...

Micron 78nm 1Gb DDR3

6

slide-27
SLIDE 27

DRAM: Micron MT47H512M4

7

slide-28
SLIDE 28

DRAM: Micron MT47H512M4

8

slide-29
SLIDE 29

DRAM Variants

  • The basic DRAM technology has been

wrapped in several different interfaces.

  • SDRAM (synchronous)
  • DDR SDRAM (double data-rate)
  • Data clocked on rising and falling edge of the

clock.

  • DDR2 -- faster, lower voltage DDR
  • DDR3 -- even faster, even lower-voltage
  • GDDR2-5 -- For graphics cards.

9

slide-30
SLIDE 30

Current State-of-the-art: DDR3 SDRAM

  • DIMM data path is 64bits

(72 with ECC)

  • Data rate: up to 1066Mhz

DDR (2133Mhz effective)

  • Bandwidth per DIMM

GTNE: 16GB/s

  • guaranteed not to exceed
  • Multiple DIMMs can attach

to a bus

  • Reduces bandwidth/GB (a

good idea?)

Each chip provides one 8-bit slice. The chips are all synchronized and received the same commands

10

slide-31
SLIDE 31

DRAM Scaling

  • Long term need for performance has driven DRAM hard
  • complex interface.
  • High performance
  • High power.
  • DRAM used to be the main driver for process scaling, now

it’s flash.

  • Power is now a major concern.
  • Scaling is expected to match CMOS tech scaling
  • F2 cell size will probably not decrease
  • Historical foot note: Intel got its start as a DRAM

company, but got out of it when it became a commodity.

11