DRAM CONTROLLER Mahdi Nazm Bojnordi Assistant Professor School of - PowerPoint PPT Presentation

DRAM CONTROLLER Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture

Overview ¨ Announcement ¤ Homework 4 will be released on Nov. 28 th ¨ This lecture ¤ DRAM control ¤ DRAM timing ¤ DRAM hierarchy n Channel, bank

Recall: DRAM System ¨ DRAM chips can perform basic operations

Recall: DRAM System ¨ DRAM chips can perform basic operations CPU Chip

Recall: DRAM System ¨ DRAM chips can perform basic operations CPU Chip DRAM Chips Memory Modules

Recall: DRAM Operations ¨ Main DRAM operations are ¤ Precharge bitlines to prepare subarray for activating a wordline ¤ Activate a row by connecting DRAM cells to the bitlines and start sensing ¤ Read the contents of a data block from the row buffer ¤ Write new contents for data block into the row buffer ¤ Refresh DRAM cells n can be done through a precharge followed by an activate

DRAM Row Buffer ¨ All reads and writes are performed through RB DRAM Cell Row Access Data Array Strobe (RAS) Column Access Row Buffer (RB) Strobe DRAM (CAS) Sense Amp.

DRAM Row Buffer ¨ Row buffer holds a single row of the array ¤ A typical DRAM row (page) size is 8KB ¨ The entire row is moved to row buffer; but only a block is accessed each time ¨ Row buffer access possibilities ¤ Row buffer hit: no need for a precharge or activate n ~20ns only for moving data between pins and RB ¤ Row buffer miss: activate (and precharge) are needed n ~40ns for an empty row n ~60ns for on a row conflict

DRAM Control ¨ DRAM chips have no intelligence ¤ An external controller dictates operations ¤ Modern controllers are integrated on CPU ¨ Basic DRAM timings are ¤ t CAS : column access strobe (RD à DATA) ¤ t RAS : row active strobe (ACT à PRE) ¤ t RP : row precharge (PRE à ACT) Row Buffer ¤ t RC : row cycle (ACT à PRE à ACT) Decoder ¤ t RCD : row to column delay (ACT à RD/WT) Data Array

DRAM Control ¨ DRAM chips have no intelligence ¤ An external controller dictates operations ¤ Modern controllers are integrated on CPU ¨ Basic DRAM timings are CPU ¤ t CAS : column access strobe (RD à DATA) DRAM Controller ¤ t RAS : row active strobe (ACT à PRE) ¤ t RP : row precharge (PRE à ACT) Row Buffer ¤ t RC : row cycle (ACT à PRE à ACT) Decoder ¤ t RCD : row to column delay (ACT à RD/WT) Data Array

Enforcing Timing

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B Cmd Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B Cmd Act X Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act X Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act Rd X A Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act Rd X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act Rd X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RAS t RCD Cmd Act Rd Pr X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B t RAS t RP t RCD Cmd Act Rd Pr X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B t RAS t RP t RCD Cmd Act Rd Pr Act X A Y Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array t RC Y B t RAS t RP t RCD Cmd Act Rd Pr Act X A Y Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer B X A Data Array t RC Y B t RAS t RP t RCD Cmd Act Rd Pr Act Rd X A Y B Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer B X A Data Array t RC Y B t RAS t RP t RCD Cmd Act Rd Pr Act Rd X A Y B Addr Data Data Data t CAS

Improving Performance DRAM Channels

Memory Channels ¨ Memory channels provide fully parallel accesses ¤ Separate data, control, and address buses Requests RD B RD A Row Buffer Row Buffer X A X Data Array Data Array Y Y B

Memory Channels ¨ Memory channels provide fully parallel accesses ¤ Separate data, control, and address buses t RCD Cmd Act Rd Requests A Addr X RD B RD A Data Data t CAS Row Buffer Row Buffer X A X Data Array Data Array Y Y B

Memory Channels ¨ Memory channels provide fully parallel accesses ¤ Separate data, control, and address buses t RCD Cmd Act Rd Requests A Addr X RD B RD A Data Data t CAS t RCD Cmd Act Rd Row Buffer Row Buffer Addr Y B X A X Data Array Data Array Data Data Y Y B t CAS

Memory Channels ¨ Memory channels provide fully parallel accesses ¤ Separate data, control, and address buses t RCD Not scalable due to pin overhead Cmd Act Rd Requests A Addr X RD B RD A Data Data t CAS t RCD Cmd Act Rd Row Buffer Row Buffer Addr Y B X A X Data Array Data Array Data Data Y Y B t CAS

Improving Performance DRAM Ranks

Memory Banks ¨ Memory banks provide parallel operations ¤ Shared data, control, and address buses ¨ The goal is to keep the data bus fully utilized Requests RD B RD A Bank 0 Bank 1 Row Buffer Row Buffer X A X Data Array Data Array Y Y B

Memory Banks ¨ Memory banks provide parallel operations ¤ Shared data, control, and address buses ¨ The goal is to keep the data bus fully utilized Requests Cmd Act Rd RD B RD A A Addr X Bank 0 Bank 1 Data Data Row Buffer Row Buffer X A X Data Array Data Array Y Y B

Memory Banks ¨ Memory banks provide parallel operations ¤ Shared data, control, and address buses ¨ The goal is to keep the data bus fully utilized Requests Cmd Act Rd Act Rd RD B RD A A Addr X Y B Bank 0 Bank 1 Data Data Data Row Buffer Row Buffer X A X Data Array Data Array Y Y B

Memory Banks ¨ Memory banks provide parallel operations ¤ Shared data, control, and address buses ¨ The goal is to keep the data bus fully utilized Requests Cmd Act Rd Act Rd RD B RD A A Addr X Y B Bank 0 Bank 1 Data Data Data Row Buffer Row Buffer X A X Shorter data transfer time to reduce bus conflicts Data Array Data Array Double data rate vs. single rate Y Y B

DRAM Organization ¨ DRAM channels are independently accessed through dedicated data, address, and command buses ¤ Physically broken down into DIMMs (dual in-line memory modules) ¤ Logically divided into ranks, which are a collection of DRAM chips responding to the same memory request DIMM Processor x8 x8 x8 x8 x8 x8 x8 x8 Memory Controller address/cmd data (64-wire)