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DRAM Dynamic Random Access Memory (DRAM) Storage Charge on a capacitor Decays over time (us-scale) This is the dyanamic part. About 6F 2 : 20x better than SRAM Reading Precharge Assert word line

  1. DRAM

  2. Dynamic Random Access Memory (DRAM) • Storage • Charge on a capacitor • Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than SRAM • Reading • Precharge • Assert word line • Sense output • Refresh data Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

  3. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor • Wordline 0 Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than SRAM • Reading Wordline 1 • Precharge • Assert word line • Sense output • Refresh data + - Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

  4. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor • Wordline 0 Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than SRAM • Reading Wordline 1 • Precharge • Assert word line • Sense output • Refresh data + - Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

  5. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor • Wordline 0 Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than SRAM • Reading Wordline 1 • Precharge • Assert word line • Sense output • Refresh data + - Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

  6. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor • Wordline 0 Decays over time (us-scale) • This is the “dyanamic” part. Bit destroyed! • About 6F 2 : 20x better than SRAM • Reading Wordline 1 • Precharge • Assert word line • Sense output • Refresh data + - Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

  7. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor • Wordline 0 Decays over time (us-scale) • This is the “dyanamic” part. • About 6F 2 : 20x better than SRAM • Reading Wordline 1 • Precharge • Assert word line • Sense output • Refresh data + - Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

  8. Dynamic Random Access Memory (DRAM) • Storage Bitline 0 Bitline 1 • Charge on a capacitor • Wordline 0 Decays over time (us-scale) • Bit Restored This is the “dyanamic” part. • About 6F 2 : 20x better than SRAM • Reading Wordline 1 • Precharge • Assert word line • Sense output • Refresh data + - Only one bit line is read at a time. The other bit line serves as a reference. The bit cells attached to Wordline 1 are not shown.

  9. DRAM: Write and Refresh Bitline 0 Bitline 1 Wordline 0 • Writing • Turn on the wordline • Override the sense amp. • Refresh Wordline 1 • Every few micro-seconds, read and re-write every bit. • Consumes power • Takes time + -

  10. DRAM Lithography

  11. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes

  12. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) Row Address • Reads and/or writes

  13. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) Row Address • Reads and/or writes

  14. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) Row Address • Reads and/or writes

  15. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes

  16. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) Column Address • Reads and/or writes

  17. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) Column Address • Reads and/or writes

  18. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) Column Address • Reads and/or writes

  19. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) Column Address • Reads and/or writes

  20. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes

  21. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes Column Address

  22. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes Column Address

  23. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes Column Address

  24. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes Column Address

  25. Accessing DRAM One DD3 8K bits DRAM bank • Apply the row address Row decoder • “opens a page” High order bits DRAM array 16k Rows • Slow (~12ns read + 24 ns precharge) • Contents in a “row Sense Amps buffer” Row Buffer • Apply one or more Low order bits Column decoder column addrs • fast (~3ns) • Reads and/or writes

  26. DRAM Devices • There are many banks per die (16 at left) • Multiple pages can be open at once. • Can keep pages open longer • Parallelism • Example • open bank 1, row 4 • open bank 2, row 7 • open bank 3, row 10 • read bank 1, column 8 • read bank 2, column 32 • ... Micron 78nm 1Gb DDR3

  27. DRAM: Micron MT47H512M4

  28. DRAM: Micron MT47H512M4

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