Memory RWM NVRWM ROM Random Non-Random EPROM Mask-Programmed - PDF document

Memory RWM NVRWM ROM Random Non-Random EPROM Mask-Programmed Access Access E 2 PROM Programmable (PROM) FLASH FIFO SRAM LIFO DRAM Shift Register CAM Memory Decoders M bits M bits S 0 S 0 Word 0 Word 0 S 1 Word 1 Word 1 A 0 S 2 Storage Storage Word 2 Word 2 N Words Cell A 1 Cell Decoder A K-1 S N-2 Word N-2 Word N-2 S N_1 Word N-1 Word N-1 Input-Output Input-Output (M bits) (M bits) N words => N select signals Decoder reduces # of select signals Too many select signals K = log 2 N 1

Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K Row Decoder Word Line A K+1 A L-1 M.2 K Amplify swing to Sense Amplifiers / Drivers rail-to-rail amplitude A 0 Selects appropriate Column Decoder word A K-1 Input-Output (M bits) Array Decoding 2

Hierarchical Memory Arrays Row Address Column Address Block Address Global Data Bus Control Block Selector Global Amplifier/Driver Circuitry I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Memory Timing Definitions Read Cycle READ Write Cycle Read Access Read Access WRITE Write Access Data Valid DATA Data Written 3

Memory Timing Approaches MSB LSB Address Row Address Column Address Bus Address RAS Address Bus Address transition CAS initiates memory operation RAS-CAS timing DRAM Timing SRAM Timing Self-timed Multiplexed Adressing Example: HM6264 8kx8 SRAM 4

HM6264 Interface Function Table 5

Timing Read Cycle 1 6

Read Cycle 1 85ns min 85ns max 85ns max 10ns min 30ns min 85ns max 10ns min 45ns max 30ns min 5ns min 30ns min 10ns min Read Cycle 2 7

Read Cycle 2 85ns max 10ns min 10ns min Write Timing 8

Write Cycle Write Cycle 85ns min 75ns min 0ns min 75ns min 55ns min 0ns min 0ns min, 30ns max 40ns min 0ns min 9

What Does All This Mean � For a read: � If you assert CS1, CS2, address, and OE all at the same time, it will be max 85ns before valid data are available at chip outputs � For a write: � You can assert CS1, CS2, address, data, and WE all at the same time if you want to � You need to wait 55ns from WE edge, or 75ns from CS1/CS2 edge for write to have happened R/W Memories In General • STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential • DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended 10

SRAM Circuits SRAM Cell, Transistors 11

SRAM, Resistive Pullups Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K Row Decoder Word Line A K+1 A L-1 M.2 K Amplify swing to Sense Amplifiers / Drivers rail-to-rail amplitude A 0 Selects appropriate Column Decoder word A K-1 Input-Output (M bits) 12

Memory Column � Each column has all the support circuits Reading the Bit � Single-ended read using an inverter � Dynamic pre-charge on the bit lines � P-types pull bit lines high 13

Reading the Bit 2 � Single-ended read using an inverter � Dynamic pre-charge on the bit lines � Note the N-types used as pull-ups Reading the Bit 3 � Differential read using sense amp � Static N-type pullup on the bit lines 14

Read Waveforms Sense Amp 15

Sense Amp Transistors Column Organization 16

Write Circuits Write Circuit Simulation 0 17

Analog Sim, Circuit WL V DD M 2 M 4 Q M 6 Q M 5 M 1 M 3 BL BL Analog Analysis, Write WL V DD M 4 Q = 0 M 6 Q = 1 M 5 M 1 V DD BL = 1 BL = 0 V DD 2 V DD 2 (W / L ) n,M 6 ≥ 0.33 ( W / L ) p,M 4 V DD V DD ⎛ ⎞ ⎛ ⎞ ( ) - - - - - - - - - - - ( ) - - - - - - - - - - - k n M6 V DD – V Tn – - - - - - - - - - - - = k p M4 V DD – V Tp – - - - - - - - - - - - ⎝ ⎠ ⎝ ⎠ , , 2 2 8 8 2 k n M5 V DD V DD 2 - V DD V DD , ⎛ ⎛ ⎞ ⎞ ⎛ ⎞ ( ) (W / L ) n,M 5 ≥ 10 ( W / L ) n,M 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - – V Tn = k n M1 V DD – V Tn – - - - - - - - - - - - ⎝ ⎝ ⎠ ⎠ , ⎝ ⎠ 2 2 2 2 8 18

Analog Analysis, Read WL V DD M 4 BL BL Q = 0 M 6 M 5 Q = 1 M 1 V DD V DD V DD C bit C bit k n M5 V DD 2 V DD 2 - V DD V DD , ⎛ ⎛ ⎞ ⎞ ⎛ ⎞ ( ) -- - -- - -- - -- - -- - - -- - -- - -- - - -- - -- - -- - -- - -- - -- - -- - -- - – V Tn = k n M1 V DD – V Tn – - - -- - -- - -- - - ⎝ ⎝ ⎠ ⎠ , ⎝ ⎠ 2 2 2 2 8 (W / L ) n,M 5 ≤ 10 ( W / L ) n,M 1 (supercedes read constraint) 6T SRAM Layout 19

Another 6T SRAM Layout SRAM bit from makemem (v1) 20

SRAM bit from makemem (v2) Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K Row Decoder Word Line A K+1 A L-1 M.2 K Amplify swing to Sense Amplifiers / Drivers rail-to-rail amplitude A 0 Selects appropriate Column Decoder word A K-1 Input-Output (M bits) 21

Row Decoders � Select exactly one of the memory rows � Simple versions are just gates Row Decoder Gates � Standard gates � Or, pseudo-nmos gates with static pull up � Easier to make large fan-in NOR 22

Pre-decode Row Decoder � Multiple levels of decoding can be more efficient layout Pre-decode Row Decoder � Other circuit tricks for building row decoders… 23

Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K Row Decoder Word Line A K+1 A L-1 M.2 K Amplify swing to Sense Amplifiers / Drivers rail-to-rail amplitude A 0 Selects appropriate Column Decoder word A K-1 Input-Output (M bits) Array-Structured Memory 24

Sharing Sense Amps Sense Amp Mux 25

Sense Amp Mux Decoded Column Decode 26

Improving Speed, Power Multi-Port Memory � Very common to require multiple read ports � Think about a register file, for example 27

Multi-Port Register Re1 Re0 � Slightly larger cell, but with single-ended read – makes a great register file Register File � Slightly larger cell, but with single-ended read – makes a great register file 28

Dynamic RAM � Get rid of the pull-ups! � Store info on capacitors � Means that stored information leaks away Dynamic RAM… � Once you agree to use a capacitor for charge storage there are other ways to build this… 29

3T DRAM Circuit BL 1 BL 2 WWL WWL RWL RWL X V DD -V T M 3 X M 2 V DD M 1 BL 1 C S Δ V BL 2 V DD -V T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn 3T DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1 30

1 T DRAM Circuit 2-T (1-T) DRAM layout � Note the increased gate size of the storage transistor � Increases the capacitance 31

1T DRAM Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD . 1T DRAM Read/Write BL WL Write "1" Read "1" WL M 1 C S X V DD − V T GND V DD BL sensing V DD /2 V DD /2 C BL Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance C S Δ V ( ) - - -- - -- - -- - -- - -- - -- - -- - - = V BL – V PRE = V BIT – V PRE C S + C BL Voltage swing is small; typically around 250 mV. 32

1T DRAM Cell “Folded bit line” Array of DRAM Cells “Folded Bit Line” 33

Reading a 1T DRAM Cell Charge Sharing DRAM Sense Amp 34

Photo of 1T DRAM Advanced DRAM Cells Try to get more capacitance per unit area… Trench Capacitor 35

Examples of Advanced DRAMs Word line Capacitor dielectric layer Cell plate Insulating Layer Cell Plate Si Transfer gate Isolation Capacitor Insulator Refilling Poly Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Trench Cell Stacked-capacitor Cell Memory Timing Approaches MSB LSB Address Row Address Column Address Bus Address RAS Address Bus Address transition CAS initiates memory operation RAS-CAS timing DRAM Timing SRAM Timing Self-timed Multiplexed Adressing 36

DRAM Interface Extended Data Out Page Mode 37

Comments on Timing Architectural Issues 38

SDRAM - Use CAS for Bursts DDR SDRAM � Double Data Rate 39

DRAM Timing RAMBUS DRAM (RDRAM) 40

RDRAM Bandwidth Maximum Bandwidth 41

Normal Bus for DRAM DIMMs RDRAM Bus 42

Deep Pipelining - High Latency RDRAM Addressing 43

Row Activate Command RDRAM System Arch 44

RDRAM Internal Arch Regular DRAM 45

Single Bank DRAM Multi-Bank DRAM 46

Peak Bandwidth ROM 47