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A 1.1V, 667MHz Random Cycle, , y , Asymmetric 2T Gain Cell Embedded DRAM with a 99 9 Percentile Retention DRAM with a 99.9 Percentile Retention Time of 110sec Ki Chul Chun Pulkit Jain Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, and Chris H.

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SLIDE 1

A 1.1V, 667MHz Random Cycle, , y , Asymmetric 2T Gain Cell Embedded DRAM with a 99 9 Percentile Retention DRAM with a 99.9 Percentile Retention Time of 110µsec

Ki Chul Chun Pulkit Jain Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, and Chris H. Kim University of Minnesota, Minneapolis, MN

Symposia on VLSI Technology and Circuits

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SLIDE 2

Outline

  • Motivation
  • Proposed Techniques for Enhancing
  • posed

ec ques o a c g EDRAM Performance

– Asymmetric 2T Gain Cell Asymmetric 2T Gain Cell – Current S/A with Pseudo-PMOS Diode Half Swing Write Bit line Driver – Half Swing Write Bit-line Driver – Stepped Write Word-line Technique

  • 65nm EDRAM Chip Measurements
  • Summary

Slide 1

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SLIDE 3

Embedded Memory Options

[1] J Barth et al ISSCC ’07 [2] D Somasekhar et al ISSCC ‘08

Slide 2

[1] J. Barth et al., ISSCC 07, [2] D. Somasekhar et al., ISSCC 08 [3] K. Chun et al., VLSI Symp. ‘09

slide-4
SLIDE 4

Random Cycle Comparison

LP 65nm 1 1V 85ºC WL enabling RBL ∆100 V (6 LP 65nm, 1.1V, 85 C

3T eDRAM

+351ps +581ps 1.83ns RBL ∆100mV (6σ) Sensing WBL driving Cell restoring (6σ)

6T SRAM

Refresh period: 100µs for 3T eDRAM 0.9ns Latency: 1.94ns Cell restoring (6σ) 0.5 1 1.5 2 2.5 3

6T SRAM

Pre-charging Latency: 1.65ns

  • Approaches to enhance eDRAM performance

0.5 1 1.5 2 2.5 3

– 6T micro sense amplifier for 1T1C eDRAMs (IBM) – Boosted 3T gain cell (Univ. of Minnesota)

Slide 3

– Asymmetric 2T gain cell (this work)

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SLIDE 5

Cell Retention Time Issue

65nm 1 1V 85ºC

1.0 1.2

65nm, 1.1V, 85ºC

0 8

Data 1 low limit t(∆BL 200mV)= 500ps

0 4 0.6 0.8

w/ 256cells/BL Read reference bias

BIAS 0.2 0.4

µs

t(∆REF 100mV)= 500ps w/ 256cells/BL

5E-5 2.5E-4 1E-4 2E-4 1.5E-4

*1M Monte-Carlo simulations (3-NMOS gain cell)

  • Small storage capacitance of a gain cell

– Rapid decrease of cell signal with large variations S d d t i i d t ‘1’ t ti t i t

Slide 4

– Speed-determining data ‘1’ retention constraint

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SLIDE 6

Rationale of Asymmetric Gain Cell

  • M. Ichihashi et al., VLSI Symp. ‘05
  • PMOS write device compensates NMOS IGATE
  • IGATE prevailing bias poor compensation
  • Goal: Keep the speed-determining data ‘1’

Slide 5

voltage close to VDD Asymmetric 2T Gain Cell

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SLIDE 7

Proposed Asymmetric 2T Gain Cell

65nm, 1.1V, 85ºC

1 2

ge (V)

, ,

0 4 0.6 1.0 1.2 0.8

VBIAS_3T

∆=0.21V

Asymmetric 3T

1.0 1.2

  • de voltag

47.4µs (BL delay=500ps)

0.2 0.4 ∆ 0 25V

Asymmetric 2T

0.2 0.4 0.6

Cell no

0.8 ∆=0.25V ∆=0.25V

VBIAS_2T 174.3µs (BL delay=300ps)

  • Data ‘1’ favorable (pull-up) leakages and low VTH

5E-5 2.5E-4

Time after write (sec)

1E-4 2E-4 1.5E-4

Data 1 favorable (pull up) leakages and low VTH storage (read) device

– 3.7X retention time improvement with 40% read bit-

Slide 6

p line delay enhancement

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SLIDE 8

Read Bit-line Leakage in 2T eDRAM

I

I I I I

I RBLB

d D)

IREAD RBL

d D)

1 ILEAK 1 ILEAK 1 ILEAK 1 ILEAK 1

d D) d D) d D)

IBIAS VBIAS

d D) d D)

RBLB S/A

Selected (GND Unselected (VDD Unselected (VDD Unselected (VDD Unselected (VDD) Selected (GND Unselected (VDD Unselected (VDD

No RBL leakage Worst RBL leakage

0 4 0.6 1.0 1.2 0.8 ∆=100mV

tage (V)

65nm, 1.1V, 100ºC, Fast RBLD0 RBL RBLREF

0 4 0.6 1.0 1.2 0.8 ∆=100mV

tage (V)

Data 1 read

RBLD0 RBLD1 RBLREF 65nm, 1.1V, 100ºC, Fast

0.2 0.4 0.5 3

Delay (nsec)

1 2 1.5

Volt

2.5 RWL enable

RBLD1

0.2 0.4 0.5 3

Delay (nsec)

1 2 1.5

Volt

2.5

Data 1 read failure!

REF

  • Very small voltage window results in read failure

in worst case scenario

Slide 7

– VDD pre-charged Current Sense-Amplifier (C-S/A)

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SLIDE 9

Previous Current S/As

E Seevinck et al VLSI Symp ‘90 J Sim et al VLSI Symp ‘02

  • Limited voltage headroom (left) and impedance

t hi i ( i ht)

  • E. Seevinck et al., VLSI Symp. ‘90
  • J. Sim et al., VLSI Symp. 02

Slide 8

matching issue (right)

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SLIDE 10

Proposed Pseudo-PMOS Diode C-S/A

IINB IIN

1 1 Read bias

RBLL Current RBLR

P1

VBB lected (GND)

1

lected (VDD)

1

lected (GND) lected (VDD) SAB SA

Pse do

P2

SAEN Se Unse Se Unse

Leakages Pseudo PMOS diode

VDD > VTH + VOV + 2VDS,SAT where, |VBB| > |VTH| Rin = (gmP2 gmP1) (gmP1)(gmP2)

  • Simple and stable impedance matching with

h d lt h d

where, |VBB| |VTH| (gmP1)(gmP2)

Slide 9

enhanced voltage headroom

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SLIDE 11

Read Bit-line Delay Comparison

) rcentile (%) Pe

  • Read bit-line delay of the proposed 2T eDRAM is

Read bit line delay of the proposed 2T eDRAM is similar to that of an SRAM

– 1Mb macro distributions with cell voltage distributions,

Slide 10

g , includes random VTH variations and C-S/A mismatches

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SLIDE 12

Half Swing Write Bit-line Driver

SA RBLL RBLR

Sense amplifier & read port

WBLR

Write-back circuit & write port

SA SA SAB VBB WBLL SAB WBLL

  • Performance advantages over conventional GND

pre-charged WBL scheme pre charged WBL scheme

– ~50% faster switching time and 25% smaller WBL charging current consumption on average

Slide 11

– 2.4% retention time improvement

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SLIDE 13

Stepped Write Word-line Technique

WWL VPP (VDD+0.3V)

WWLB ADDR RSET

  • Boosted high (VPP) and low (VBB) supplies are

PDNGND PUPVDDB

Boosted high (VPP) and low (VBB) supplies are standard in DRAMs to prevent signal loss

  • Two step WWL to reduce charge pump overhead

Two step WWL to reduce charge pump overhead

– 67% power saving of boosted supplies and 4.4% chip size reduction compared to level shifters

Slide 12

– Narrow WWL pulse width (-25%) issue

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SLIDE 14

Write Performance Comparison

(%)

rent (A)

Percentile (

V) Cur

P

Voltage (V

  • Write device of a gain cell is a simple pass gate

V

Write device of a gain cell is a simple pass gate

– Excellent data ‘1’ write margin crucial for read – Sufficient WWL window for data ‘0’ (required = 179ps,

Slide 13

( q p , achieved = 406ps @ 667MHz random cycle)

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SLIDE 15

192kb Test Macro Architecture

  • 192 cells per WL, 512 cells per split BL

architecture which share common BL-S/A and

Slide 14

write driver

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SLIDE 16

EDRAM Test Chip Microphotograph

SA & WBACK

LUMN DECODER

BLS

COL CTRL

  • 667MHz random cycle at a 110μsec retention time

and a 99.9% bit yield condition

Slide 15

  • Retention time increases to 1200μsec for 500MHz
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SLIDE 17

Automated Retention Time Measurement

  • Measurement bench: LabViewTM controlled

pattern generator and logic analyzer (left)

  • Measured retention time bitmap of a 1kb sub-

Slide 16

array at 1.5ns random cycle time (right)

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SLIDE 18

Impact of VPP Level on Retention Time

100 60 80 100 Data 1 with increasing VPP 1.1V, 85ºC VPP=1.4~1.6V, 0.05V step 20 40 increasing VPP 1.E+02 1.E+03 1.E+04

Retention time (µsec)

Data 0

  • Strong VPP dependency of retention time can be

exploited for exploited for

– Finding optimal retention time considering both data ‘0’ and data ‘1’ cases

Slide 17

– Post-fabrication trimming to cope with D2D variations

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SLIDE 19

Random Cycle Time Measurement

(µsec)

3 4 1.E+03 1.E+04

me (nsec) (µsec) 99.9% bit yield at 85ºC ntion time (

2 1.E+02

m cycle tim ntion time Reten

1 0 8 0 9 1 1 1 1 2 1 3 1 4 1.E+00 1.E+01

Random Reten Cycle time Retention time

  • 667MHz (500MHz) random cycle and 110µs (1200µs)

0.8 0.9 1 1.1 1.2 1.3 1.4

VDD (V)

retention time at 1.1V, 85°C, and 99.9% bit yield condition (left) Wid ti lt f 0 8V 1 4V ( i ht)

Slide 18

  • Wide operating voltage range of 0.8V ~ 1.4V (right)
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SLIDE 20

Summary (1/2)

  • Gain cell eDRAM as an alternative for high

density memory

– 2.4X higher bit cell density than SRAM – Generic logic process and decoupled read/write path enables the potential of better performance than 1T1C enables the potential of better performance than 1T1C eDRAM

  • Proposed circuit techniques to improve read

p q p speed and enhance retention time

– Asymmetric 2T Gain Cell – Current S/A with Pseudo-PMOS Diode – Half Swing Write Bit-line Driver St d W it W d li T h i – Stepped Write Word-line Technique

Slide 19

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SLIDE 21

Summary (2/2)

  • A 1.1V, 65nm 192kb eDRAM chip with 512 cells

per BL architecture demonstrated

– 667MHz random cycle at 1.1V, 85°C, and a 99.9% retention time of 110μsec – 248μW per Mbit static power dissipation at 1 2V 85°C 248μW per Mbit static power dissipation at 1.2V, 85 C, 500MHz random cycle and 1200μsec retention time – Measured latencies are 1.39ns/1.65ns at 1.2V/1.1V, 85°C

Acknowledgements: Broadcom, a Scholarship from Samsung Electronics, and an IBM Faculty Partnership Award Partnership Award

Slide 20