Distributed, virtual and real debugging of a MIPS SoC Martin - - PowerPoint PPT Presentation

▶
distributed virtual and real debugging of a mips soc
SMART_READER_LITE
LIVE PREVIEW

Distributed, virtual and real debugging of a MIPS SoC Martin - - PowerPoint PPT Presentation

Oct 23, 2023 525 likes •825 views

Distributed, virtual and real debugging of a MIPS SoC Martin Strubel section5.ch Distributed, virtual and real debugging of a MIPS SoC Martin Strubel section5.ch 02/2013 Distributed, Flight plan virtual and real debugging of a MIPS

slide-1
SLIDE 1

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Distributed, virtual and real debugging of a MIPS SoC

Martin Strubel section5.ch 02/2013

slide-2
SLIDE 2

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Flight plan

1 Debugging a complex FPGA design (in theory)

❼ A SoC (System on Chip) example ❼ MAIS: A portable MIPS soft core by Ren´

e Doss

❼ The Test Access Port (TAP): A generic debug interface

2 Virtualizing the hardware

❼ ’Model in the loop’ techniques ❼ Making real software speak to virtual hardware

3 Demos

❼ Debugging the virtual chip ❼ Debugging the real hardware

slide-3
SLIDE 3

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

The challenge

Debug this:

Figure: Somewhat unreadable schematic

slide-4
SLIDE 4

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Divide et impera

Figure: Simplified SoC schematic with Debug port

slide-5
SLIDE 5

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Existing solutions

Proprietary solutions from various FPGA vendors: Signal inspection tool Soft CPU core Vendor ChipScope microblaze Xilinx Reveal mico32 Lattice SignalTap NiosII Altera

Table: Tool examples ❼ Virtualization capabilities depend on second party

simulation tools (✩✩✩-✩✩✩✩✩)

❼ Debug port itself can sometimes not be simulated ❼

slide-6
SLIDE 6

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Existing solutions

Proprietary solutions from various FPGA vendors: Signal inspection tool Soft CPU core Vendor ChipScope microblaze Xilinx Reveal mico32 Lattice SignalTap NiosII Altera

Table: Tool examples ❼ Virtualization capabilities depend on second party

simulation tools (✩✩✩-✩✩✩✩✩)

❼ Debug port itself can sometimes not be simulated ❼ No easy DIY virtualization of the hardware due to

proprietary and closed libraries.

slide-7
SLIDE 7

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

The MIPS-compatible MAIS CPU

Introducing a soft cpu core may speed up proto- typing/debugging.

(exercised previously with ZPU soft core)

Why MIPS?

❼ Well-established architecture with many derivatives

(Loongson SoC, Router chipsets)

❼ Fast, easy to implement, resource saving ❼ Actively maintained tool chain and emulators ❼

❼ ❼

slide-8
SLIDE 8

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

The MIPS-compatible MAIS CPU

Introducing a soft cpu core may speed up proto- typing/debugging.

(exercised previously with ZPU soft core)

Why MIPS?

❼ Well-established architecture with many derivatives

(Loongson SoC, Router chipsets)

❼ Fast, easy to implement, resource saving ❼ Actively maintained tool chain and emulators ❼ MAIS design by Ren´

e Doß:

❼ Well-portable MIPS 32 bit implementation ❼ Access to VHDL sources

slide-9
SLIDE 9

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

In Circuit Emulation (ICE)

In emulation mode, the CPU...

❼ takes opcodes from the EMUIR register ❼ executes them when it gets an emuexec pulse ❼ exchanges data with the debugger via the EMUDATA

register

slide-10
SLIDE 10

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

In Circuit Emulation (ICE)

In emulation mode, the CPU...

❼ takes opcodes from the EMUIR register ❼ executes them when it gets an emuexec pulse ❼ exchanges data with the debugger via the EMUDATA

register Full remote control of the CPU via a test access port (TAP)!

slide-11
SLIDE 11

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Debugger components

1 The developer’s front end:

The GNU debugger (gdb)

Figure: GDB

Debugger connects to back end via a TCP remote debugging

  • protocol. Means: Distributed across networks!
slide-12
SLIDE 12

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Debugger components

1 The developer’s front end:

The GNU debugger (gdb)

2 The back ends: 1 uniproxy: a JTAG

debug server

2 qemu: a MIPS CPU

emulator Figure: GDB and uniproxy

Debugger connects to back end via a TCP remote debugging

  • protocol. Means: Distributed across networks!
slide-13
SLIDE 13

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Debugger components

1 The developer’s front end:

The GNU debugger (gdb)

2 The back ends: 1 uniproxy: a JTAG

debug server

2 qemu: a MIPS CPU

emulator

3 JTAG debugger hardware:

USB JTAG adapter

Figure: ICEbear JTAG adapter

Debugger connects to back end via a TCP remote debugging

  • protocol. Means: Distributed across networks!
slide-14
SLIDE 14

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Virtualize the hardware

❼ qemu: software-emulated MIPS CPU – a functional

model

❼ Write C code to functionally emulate attached hardware

❼

❼ ❼

slide-15
SLIDE 15

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Virtualize the hardware

❼ qemu: software-emulated MIPS CPU – a functional

model

❼ Write C code to functionally emulate attached hardware

❼ VHDL simulation: cycle accurate – a timing model

❼ Typically: Simulation of logical behaviour ❼ Somewhat precise waveform output

slide-16
SLIDE 16

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Virtualize the hardware

❼

❼

❼ VHDL simulation: cycle accurate – a timing model

❼ Typically: Simulation of logical behaviour ❼ Somewhat precise waveform output

Figure: Timing accurate simulation

slide-17
SLIDE 17

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Make ants meet Make antz meet...

Drawing by Britta Schneider

slide-18
SLIDE 18

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Now seriously: make ends meet

Task: Make real world software speak to virtual hardware. Result: ghdlex OpenSource simulator extension library:

❼ Describe virtual board in

XML − →

❼ Attach virtual components

in HDL design:

❼ JTAG debugger ❼ shared RAM ❼ USB FIFO ❼ I/O pins, registers

Figure: XML hardware description

slide-19
SLIDE 19

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Virtual Hardware

VHDL-Simulation, unit under test netpp.vpi netpp client Virtual hardware driver ghdlex library JTAG processor (VHDL) Virtual USB-FIFO Virtual JTAG debugger

Virtual pins Virtual RAM

User program GNU debugger

Virtual Hardware Client/Driver Software

slide-20
SLIDE 20

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Virtual Hardware

VHDL-Simulation, unit under test netpp.vpi netpp client Virtual hardware driver ghdlex library JTAG processor (VHDL) Virtual USB-FIFO Virtual JTAG debugger

Virtual pins Virtual RAM

User program GNU debugger

Virtual Hardware Client/Driver Software

Expose design components to the network!

slide-21
SLIDE 21

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Distributed processing

Simulation Windows PC, Driver software Camera (Data acquisition) Developer, Debugger front end Embedded device

JTAG

ghdlex speaks netpp (network property protocol), therefore things can run anywhere.

❼ HDL-Simulation on powerful main frame ❼ Data routing from real world software on Windows PC to

simulation

❼ Debugger (Laptop) connecting to any of the debug servers

slide-22
SLIDE 22

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Now, where’s the bug?

❼ Bug could sit:

❼ .. in peripheral access (HDL design), or the CPU ❼ .. in SoC firmware (Code running on CPU core) ❼ .. in host (PC) software ❼ ❼

❼

❼ ❼ ❼ ❼

slide-23
SLIDE 23

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Now, where’s the bug?

❼ Bug could sit:

❼ .. in peripheral access (HDL design), or the CPU ❼ .. in SoC firmware (Code running on CPU core) ❼ .. in host (PC) software ❼ .. in Debugger components itself (reserve many gaelic curses) ❼ .. between two human ears

❼

❼ ❼ ❼ ❼

slide-24
SLIDE 24

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Now, where’s the bug?

❼ Bug could sit:

❼ .. in peripheral access (HDL design), or the CPU ❼ .. in SoC firmware (Code running on CPU core) ❼ .. in host (PC) software ❼ .. in Debugger components itself (reserve many gaelic curses) ❼ .. between two human ears

❼ Avoid to introduce bugs during development:

❼ Verify CPU behaviour against qemu (functional

simulation)

❼ Keep device configuration in exactly one XML file ❼ Use Makefile rules or similar to keep source and generated

files in sync (→ GNU make)

❼ Introduce detection mechanisms: ID codes or functionality

descriptors (JTAG USERCODE register)

slide-25
SLIDE 25

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Hands on!

Demos:

1 Debugging the simulation 2 Debugging the hardware: HDR-60 FPGA camera kit 3 Verifying the CPU using qemu

slide-26
SLIDE 26

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Hardware Test Bench

32 bit CPU core

L1 instr Bank A/B L1 data Bank A L1 data Bank B L1 cache Bank C 32 bit bus 32 bit instruction bus Core Event Controller SMMU FliX DSP JPEG encoder USB FIFO (FX2) MUX FIFO 16 bit DMA Control bus (MMR) DMA Controller

isochronous USB EP (in) FPGA

Figure: JPEG encoder test bench

slide-27
SLIDE 27

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

Final notes

❼ Questions? ❼ More about device hardware XML description:

→ http://www.section5.ch/netpp

❼ Don’t miss Ren´

e’s Introduction to his Mais MIPS core (later today in this session) Thank you for listening!

slide-28
SLIDE 28

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

StdTAP: The ’standard test access port’

The interface between the JTAG port and the CPU: a somewhat generic HDL library.

❼ Vendor independent interface (’standard’ register set) ❼ Supports Xilinx and Lattice native JTAG components ❼ CPU core architecture independent ❼ Software support by emulation library (Python, uniproxy

debug server)

slide-29
SLIDE 29

Distributed, virtual and real debugging

  • f a MIPS

SoC Martin Strubel section5.ch

TAP registers

Register Description Signals EMUSTAT ICE and CPU state emuack, emurdy, state EMUCTRL ICE control emurequest, (emuexec) EMUIR ICE instruction register 32 bit (to core) EMUDATA ICE data register 32 bit (from core)

Table: TAP registers

Actual register addressing is TAP (FPGA family) specific