Digital System-On-Chip components at ESA components at ESA ASIC - - PowerPoint PPT Presentation
Digital System-On-Chip Digital System-On-Chip components at ESA components at ESA ASIC technology platforms and converters Standard microprocessor components Components with dedicated DSP function Roland Weigand, Laurent Hili European Space
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(1) 14. Oct 2011
Roland Weigand, Laurent Hili European Space Agency Microelectronics Section MEWS 24, Tsukuba, Japan
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(2) 14. Oct 2011
– Current technologies (180 – 150 nm) – New technologies: 90 nm (UMC), 65 nm (ST) – Converters: ADC, DAC, HSSL
– LEON2: AT7913E, AT697 – LEON3: SCOC3 – LEON4: NGMP – QUADLION
– FFTC: Fast Fourier Transform Co-processor – AGGA4: GNSS baseband processor for GPS, Galileo, Glonass, Compass – CWICOM: CCSDS Wavelet Image Compression ASIC – HPDP: High Performance Data Processor – Smart image sensors for sun-sensors and star-trackers
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(3) 14. Oct 2011
ESTEC
HQ ESAC ESOC ESRIN
2251 staff in total
1310 staff 293 staff 368 staff 207 staff 73 staff European Space Research and Technology Centre R&D, engineering and test centre
The ESA Microelectronics Section http://www.esa.int/TEC/Microelectronics 8 permanent staff Directorate of Technical and Quality Management Electrical Engineering Department Data Systems Division
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(4) 14. Oct 2011
– High total dose tolerance, mixed signal capability available – Area and power consuming library, limitations in memory compiler – 90 nm planned, but funding currently on-hold
– Mixed signal, 5V IO and NVM available, no radiation hardened library – ESCC Space process capability study with DLR and Tesat http://www.dlr.de/qp/en/desktopdefault.aspx/tabid-3091/4699_read-6881/ → LFoundry Germany seems to be bankrupt → activity on hold ?
– SEU hardened library available for 180 nm, 130 nm in preparation – Mixed signal capability, embedded NVM TBD – Device qualification possible (MIL-STD-883 lot acceptance) – Export licence and commercial availability to be clarified
– Mixed signal, 5V IO and NVM available – Radiation hardened standard cell library currently not available – No space experience so far, but radiation evaluation and rad-hard library planned
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(5) 14. Oct 2011
Deep Sub Micron ASIC technologies are key for establishing European capabilities in the domain of:
Digital telecom payloads
Improve European competitiveness on mobile processors and digital sub channelisers (narrowband processors) Enable technology for future multimedia satellites and flexible payloads with active antennas (broadband processors)
Earth Observation payloads
SAR, altimetry, interferometry Mass memories High Speed Serial Links (HSSL > 1Gbps)
Navigation payloads
Wideband signal generation
The DSM programme is managed and co-financed by ESA and CNES
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(6) 14. Oct 2011
future broadband and versatile payloads (mobile, multimedia, HDTV)
– 20 … 30 Millions gates – Higher clock data path (≥ 400 MHz) – Higher power dissipation per ASIC (≥ 15 Watts) – Higher pin count package (flip chip ≥ 1600 pins) – Higher data rate interfaces (HSSL 6.25 Gbps)
– Analog input bandwidth 500 MHz instead of 150MHz – ADC and DAC data rate ≥ 1.5 Gsamples/s – High complexity antenna systems / beamforming » Number of ADC ≥ 200 » Number of DAC ≥ 200 – Need to reduce the power consumption per converters » Max power per ADC ≤ 1.5 Watt » Max power per DAC ≤ 1.5 Watt
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(7) 14. Oct 2011
ADC DAC 12b 12b 12b 12b SERDES 6.25 Gbps High Speed Serial Link (6.25 Gbps) ASIC (65 nm) Baseband processing
2 x 750 Msps 2 x 750 Msps Broadband / low power ADC 1.5 Gsps Broadband / low power DAC 1.5 Gsps Quatuor device (65 nm) Quad high speed link 4 x 6.25 Gsps Quatuor device (65 nm)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(8) 14. Oct 2011
Features (EV10AS180): 10 bits ADC integrated 1:1/2/4 Demux (selectable) 2.2 Gsps conversion rate (full BW) 1.7 Watt low latency 4 clock cycles LVDS outputs 0.5 Vpp differential input (100 ohms) Power supplies: 5.2V, 3.3V and 2.5V Ci-CGA225 package B7HF200 SiGeC technology from Infineon Performances Single Tone Performance @ Fs=1.5Gsps : SFDR = -60 dBFS, ENOB = 8.5 Bit; SNR = 55 dBFS at Fin = 750 MHz @-12 dBFS SFDR = -60 dBFS, ENOB = 8.4 Bit; SNR = 53 dBFS at Fin = 1800 MHz @-12 dBFS Broadband Performance: NPR = 44 dB at -13 dBFS Optimum Loading Factor in 1st Nyquist NPR = 43 dB at -13 dBFS Optimum Loading Factor in L-band 100 Krads radiation tolerant
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(9) 14. Oct 2011
Features (EV12DS130): 12 bits DAC integrated parallel Mux 4:1 / 2:1 (selectable) 3Gsps conversion rate 6GHz analog output BW 1.3 Watt low latency 4 clock cycles NRZ, RTZ, narrow RTZ, RF modes LVDS inputs 1 Vpp differnetial output (100 ohms) Power supplies: 3.3V digital, 3.3V and 5V analog Ci-CGA225 package B7HF200 SiGeC technology from Infineon Performances NPR @ -14dB loading factor, Fs = 3Gsps 1st Nyquist (NRZ/NRTZ) NPR=49db ENOB=9.7 bits 2nd Nyquist (NRTZ/RTZ) NPR=44db ENOB=8.8 bits 3rd Nyquist (RF) NPR=42db ENOB=8.4 bits 100 Krads radiation tolerant This activity is under CNES contract
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(10) 14. Oct 2011
Comparison between NRZ, NRTZ, RTZ and RF modes Max output power versus frequency over the 3 Nyquist zones
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(11) 14. Oct 2011
– Dual / Triple Gate Oxides – Dual / Triple Threshold Voltages for MOS Transistors – 7-9 Full Copper Dual Interconnect Levels – Low K
– 750 kgates/mm2 – 2GHz stdcells – 5.7nW/(MHz x gates) – 1.25-7.5GBit/s HSSL modules
ST Rad Hard offer based on CMOS 65nm-LP commercial process Reliability and Radiation maximisation performed at design stages
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(12) 14. Oct 2011
Systematic application of ST Design-in-Reliability (DiR) methodology (focusing HCI and NBTI) with dedicated tools for aging simulations
the product value chain.
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(13) 14. Oct 2011
– No current increase seen up to 100krad(Si) TID
– Usage of existing Robust cells, TMR – Hardening of clock-trees against SETs – Shadowing of configuration registers + scrubbing – Development of Rad-Hard new cells – Layout techniques
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(14) 14. Oct 2011
Skyrob (Rad Hard) Skyrob (Fast) Corelib (Commercial) SEU rate seu/bit/day (Geo) shielding 100mils Al 1E-9 Robust x250 1.8E-9 Robust x110 2E-7 Timing Set-up + delay (ps) 750 50% slower 500 As fast 500 Area um2 26 X2 area 23 X1.7 area 13 Energy pJ 4 X1.8 3.8 X1.7 2.2 Comparison for a DFFX3 (drive 3)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(15) 14. Oct 2011
– IP core – Device 4 x 6.25 Gbps (Quatuor)
– BER < 10-14 – 1.25 Gbps to 6.25 Gbps – Differential CML input / output (serial interface) – 4 TAP programmable pre-emphasis – 4 TAP adaptative decision feedback equaliser (DFE) – Clock data recovery for pleisio synchronous operations – JTAG & BIST (PRBS for auto test)
– LVDS parallel interface 2 x 12 bits + 1 Data Ready – 8b/10b encoder – Up to 25 Gbps aggregated data rate (half duplex) – Supply voltages 1.2V and 2.5V – Sampling clock from 150 MHz to 1.5GHz – Power ~ 1W (worst case)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(16) 14. Oct 2011
20 40 60 80 100
10 20 30 40
49krad 154krad
Recovery after annealing
SER Data 16b/20b encoder SE R Clk Framing / Stamping / CRC calculatio n 6.25Gbps ADC 10/12bits 1.5Ghz 16 bits 20 bits 2 wires ~ Pll Sampling clock Reference clock QUATUOR Div4 2 Phases Elastic Buffer Synch 4 x 4 x 48 bits SER Data 6.25Gbps 16 bits 20 bits 2 wires SER Data 6.25Gbps 16 bits 20 bits 2 wires SER Data 6.25Gbps 16 bits 20 bits 2 wires 12 bits 12 bits Datardy lvds Port A Lvds/Reg Port B Lvds/Reg Bus / Speed aligner 4x48 bits 24 bits 24 bits 9.37- 93.75Mhz MCLK 312.5 Mhz Div4 (12 or 8 bits) 37.5-375Mhz 16b/20b encoder 16b/20b encoder 16b/20b encoder Serdes S7
25 Gbps aggregated data rate Receiver eye diagram opening ENEA test campaign December 2009 Device fully operational at 200 Krads
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(17) 14. Oct 2011
TC1 (rad hard library):
TC2 (PLL 1st type):
covering frequency range from 100MHz … 1 GHz
TC3 (high speed serial link / HSSL):
TC4 (commercial library subset):
(extracted from CoreLib standard voltage)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(18) 14. Oct 2011
– Standards cells library definition done – Macros definition done – 1st library test vehicle (std cells) manufactured & preliminary characterised – 2nd library test vehicle planned for Q3/11 – 3rd library test vehicle (final version) planned for Q1/12 – Planned in 2012, ESCC evaluation of library without package – Planned in 2012, design & prototyping of the high pin count flip chip package ~ 1600 pins
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(19) 14. Oct 2011
– 1st prototype manufactured – Preliminary electric & radiation tests performed but not fully conclusive – 2nd prototype redesign & manufacturing planned in 2012 – 2nd prototype ESCC evaluation planned ~ Q4/12
– Full electric characterisation done – ESCC evaluation on the way, planned to complete in Q1/12 – Objective 2012 to get the device registered in EPPL
– Full electric characterisation done – ESCC evaluation on the way, planned to complete in Q1/12 – Objective 2012 to get the device registered in EPPL
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(20) 14. Oct 2011
Heavy Ion test campaign planned with Atmel
BepiColombo, SolarOrbiter
http://www.atmel.com/dyn/products/product_card.asp?part_id=4595 http://microelectronics.esa.int/components/AT7913E_UserManual-2-4.pdf
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(21) 14. Oct 2011
500 nm technology, ~ 3000 FM orders (2003 – 2011), still in use
MQFP256, LGA349 MCGA not available any more
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(22) 14. Oct 2011
FF1 FF2 FF3 Majority Voter Q1 Q2 Q3 clock tree 3 clock tree 2 clock tree 1 D1 D2 D3 clk D Q
clk2 clk1 clk3 SET pulse SET latched into FF1 only Q remains at correct value
Triplicated clock tree and skewed clocks
by skewing the clocks, a glitch at D is latched at most in one of the 3 FF
Q = (Q1 and Q2) or (Q2 and Q3) or (Q1 and Q3)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(23) 14. Oct 2011
http://www.astrium.eads.net/node.php?articleid=5360
– LEON3FT @ 80 MHz, GRFPU – CCSDS TM/TC interface with X-strapping interface – SpaceWire, 1553, CAN, UART – Dual AMBA-AHB bus architecture – Dual PROM/SRAM/SDRAM interface – Basic SW development (BSP/drivers) ongoing ECSS pre-qualification planned – SW tools (simulator, IDE) available – Data-sheet/user manual available on request – To be established as standard component, commercialised by Astrium France – FPGA-based Evaluation board (STARKIT) developed under CNES contract – First missions: SEOSAT, ASTROTERRA (SPOT 6/7) CSO (3 French military satellites), KRS (Kazakhstan) – Atmel 180 nm (1.8 Mgates + 2.2 Mbit memory) – Package: LGA472 with 6-sigma columns (currently assembled in the US, to be transferred to Europe)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(24) 14. Oct 2011
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(25) 14. Oct 2011
NGMP: ESA's Next Generation Microprocessor
DSU, trace buffers on PCI/AHB, performance counters
Target technology: 65 nm ST-Microelectronics
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(26) 14. Oct 2011
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(27) 14. Oct 2011
NGMP detailed block diagram part 1 (left side)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(28) 14. Oct 2011
NGMP detailed block diagram part 2 (right side)
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(29) 14. Oct 2011
NGMP: ESA's Next Generation Microprocessor (status & roadmap)
– ALR Pouponnot: “A Giga INstruction Architecture (GINA)”
– PDR (verified VHDL-RTL) achieved in December 2010 – Preliminary Datasheet and Verification Report available http://microelectronics.esa.int/ngmp/ngmp.htm – FPGA prototypes on various boards available to the user community – Development of SW environment (BSP, compiler, GRMON)
– Prototypes / evaluation boards available in Q3 2012 – Target technology eASIC Nextreme-2 ( 45 nm structured ASIC) – Implementation at target speed (goal 400 MHz)
– Radiation testing and functional validation – Schedule uncertain, waiting for the ST 65 nm space library
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(30) 14. Oct 2011
→ differences in max clock frequency (NGMP = 400 MHz) to be considered
improved cycles per instruction (CPI) good scaling
threaded benchmarks (4 cores) → almost x4
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(31) 14. Oct 2011
– 4 parallel Radix-2 FFT butterfly engines @ 128 MHz – ALU with ADD / SUB / MULTIPLY / Conjugate operations @ 128 MHz – Various combinations possible between FFT and ALU operations – Data paths in complex double-precision floating point arithmetic – 64-bit input and output data ports and 4 parallel 57-bit SDRAM ports @ 100 MHz – Conversion between various integer and floating point formats at each data port – Cross-bar switch allowing concurrent data streams between data ports and processor – EDAC protection on internal/external memories, SEU hardened flip-flops/latches – 1 kpoint complex FFT in 10 µs, 1 Mpoint complex FFT in 21 ms – 100 Msamples/sec sustainded throughput
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(32) 14. Oct 2011
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(33) 14. Oct 2011
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(34) 14. Oct 2011
which was used in GRAS (GNSS Receiver for Atmospheric Sounding) on METOP
– LEON2-FT with standard peripherals (SpW, MIL1553, UART, PIO, SPI, Timers) – GNSS front-end module allowing to connect 4 antennas with digital beamforming – FFT processing module for fast acquisition to resolve Doppler uncertainty – 36 single-frequency / dual-code GNSS base-band channels, containing each of them: – Final downconversion with code/carrier NCOs – 5 complex (I/Q) correlators per channel: 5 ( EE, E, punctual, L, LL) for BOC tracking – Code generators with LFSR (required for very long codes e.g. GPS L2CL) and code memories (required for Galileo and other signals) – Code/carrier loop aiding unit to compensate Doppler drift
– Commercialisation as standard component – Atmel 180 nm, ~ 3.5 Mgates logic (pre-layout, 140000 FF/latches), 878 Kbit memory – Package MQFP 352 – Tapeout planned in Q4 / 2011
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(35) 14. Oct 2011
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(36) 14. Oct 2011
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(37) 14. Oct 2011
– Gravity and magnetic field missions – Relative positioning – Interferometry – Altimetry
– measure Doppler shift – derive bending of GNSS signal by refraction in the atmosphere – derive vertical profiles (temperature, pressure, humidity)
Digital System-On-Chip components at ESA MEWS 24
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(38) 14. Oct 2011
– Implements CCSDS Wavelet Image Compression Standard 122.0-B-1 – Output data according to CCSDS packet protocol CCSDS 133.0-B-1 – Lossless and lossy compression @ 60 Mpixels/sec (64 MHz clock) – Spacewire and SPI serial links as command (and slow data) interfaces – 16-bit parallel interfaces (1 pixel per clock cycle) for video input and output data – Atmel 180 nm, 1.1 Mgates logic (32769 flip-flops) 4.4 Mbit on-chip RAM (68 instances) – First layout ongoing, tapeout Q4 / 2011 – Commercialisation as standard ASIC
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(39) 14. Oct 2011
Astrium Germany and ISD Greece
– Based on PACT XPP III Array Processor ( http://www.pactxpp.com/ ) – More than 5 Giga operations per second – 40x 16-bit ALU Elements @ 100 MHz – 2x Harvard type VLIW 16-bit processor cores (FNCs) running at 50MHz – 256 Kbit high-speed on-chip RAM with EDAC – External SRAM/SDRAM interface with EDAC, bandwidth of up to 200 Mbyte/s – 4 x 1.6 Gbit/s Streaming Ports – 3 SpaceWire interfaces @ 100 Mbps – SW tools: SDE, cycle accurate simulator, graphical debugging tools, libraries/APIs
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
ESA UNCLASSIFIED –For Official Use
(40) 14. Oct 2011
Smart CMOS Image sensors for Sun Sensors and Star Trackers
Development with CMOSIS, Belgium, BAE Systems and Selex Galileo
(CIS) with DARE digital library
– Plug & play: finds the sun by itself – TID hard pixel array – Windowing for object tracking – Defect pixel filtering – Image pre-processing (background subtraction, thresholding, object clustering, centroiding...) – Spacewire interface – On-chip regulators and oscillator (single 5V supply)
enhanced processing – EM = 2014, FM = 2016
Digital System-On-Chip components at ESA MEWS 24
Microelectronics Section
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(41) 14. Oct 2011
Acknowledgements to companies and colleagues which are involved into the developments for having supplied inputs for this presentation:
– For the DSM/ADC/DAC programme: ST Microelectronics, E2V and CNES ( Florence.Malou [at] cnes.fr, Jean-Louis.Venturin [at] cnes.fr ) – AT7913E: RUAG Sweden, Aeroflex Gaisler, Atmel, Jørgen Ilstad ( Jorgen.Ilstad [at] esa.int ) – AT697: Atmel France ( sparc-applab.hotline [at] nto.atmel.com ) – SCOC3: Astrium France Elancourt ( products [at] astrium.eads.net ) – NGMP: Aeroflex Gaisler Sweden ( info [at] gaisler.com ) – FFTC: Astrium Germany, Eonic and Martin Süß ( Martin.Suess [at] esa.int ) – AGGA4: Astrium Germany, Josep Roselló Guach ( Josep.Rosello [at] esa.int ) – CWICOM: Astrium France/Germany, Raffaele Vitulli ( Raffaele.Vitulli [at] esa.int ) – HPDP: Astrium Germany, ISD Greece, Roland Trautner ( Roland.Trautner [at] esa.int ) – SSOC: CMOSIS Belgium, Stephen Phil Airey ( stephen.airey [at] esa.int )
Further information can be obtained from the contact e-mails mentioned hereabove, or from the authors of this presentation
– Roland Weigand ( Roland.Weigand [at] esa.int ), Laurent Hili ( Laurent.Hili [at] esa.int )