Development of readout test system for prototype ASIC of pixel - - PowerPoint PPT Presentation

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Development of readout test system for prototype ASIC of pixel - - PowerPoint PPT Presentation

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Kuno and Yamanaka Group Year-End Presentation 2017 Development of readout test system for prototype ASIC of pixel detector for ATLAS upgrade ATLAS ASIC

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28/12/2017 Osaka University M2 Yasunori Sawada

Kuno and Yamanaka Group Year-End Presentation 2017

ATLASアップグレード用ピクセル検出器の
 プロトタイプASIC読み出し試験システムの開発

Development of readout test system 
 for prototype ASIC


  • f pixel detector for ATLAS upgrade
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Kuno and Yamanaka Group Year-End Presentation 2017

Overview

1.ATLAS Experiment 2.HL-LHC ATLAS Pixel 3.Pixel ASIC 4.ASIC Readout system 5.Summary

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Kuno and Yamanaka Group Year-End Presentation 2017

1.ATLAS Experiment - HL-LHC

  • HL-LHC ATLAS - 2026~
  • Energy - 14 TeV
  • Luminosity - ~7.5×1034 cm-2s-1

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Kuno and Yamanaka Group Year-End Presentation 2017

2.HL-LHC ATLAS Pixel detector

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ASIC

(Application specific integrated circuit)

Semiconductor Sensor Detect charged particles Digitization of signal & some functions

e- e- e- e- h+ h+ h+ h+

Si FPGA Board

(Field programmable gate array)

Data processing, PC Interface …etc

0111011011111….

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Kuno and Yamanaka Group Year-End Presentation 2017

2.HL-LHC ATLAS Pixel detector

  • Pixel hit rate in HL-LHC ~ average 100-150
  • Requirements
  • Matrix size : 400×384
  • Pixel pitch : 50×50μm2
  • Trigger rate : 


1 MHz (w/ <35μs latency)

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→ Development ASIC, RD53 Collaboration ~100 Hits/event × 26 bit/Hit × 1 MHz →~2.6 Gbps

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SLIDE 6

Kuno and Yamanaka Group Year-End Presentation 2017

3.Pixel ASIC - RD53A

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  • Prototype ASIC RD53A

  • Half size of production
  • ATLAS Japan group

  • Radiation tolerance test

  • Test beam
  • Required performance

  • Readout bandwidth : ~5 Gbps/chip

Demand for Data acquisition system development !

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Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System

  • 1. FE-I4 Readout system using Ethernet
  • 2. FE-I4 Readout system using PCI Express

  • 3. RD53A Readout system using PCI Express


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{

Development milestones

  • FE-I4 - Currently used ASIC in ATLAS Pixel

Xilinx KC705 Evaluation Board

High speed

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SLIDE 8

Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System - Ethernet

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  • 1. FE-I4 Readout system using Ethernet

Trigger &Command Computer Readout ASIC SiTCP Serial→Parallel Ethernet (UDP/IP, TCP/IP)

< 1Gbps

40 MHz 160 Mbps

8Bit→10Bit

Clock

FIFO

  • Implemented in commercially available board !
  • Not support 5 Gbps readout, but enough for FE-I4 x4~x6(?)

80 MHz

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Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System - Ethernet

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  • 1. FE-I4 Readout system using Ethernet
  • Operation Test
  • Tuning of thresholds for Hit
  • Tuning of ToT (like ADC Value) to each pixel

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 Threshold [e] 20 40 60 80 100 120 140 160 180 200 # pixels

Target threshold : 3600e Blue : Before tuning Red : After tuning

Threshold [e] # Pixels

2 4 6 8 10 12 14 16 ToT 50 100 150 200 250

Target ToT : 10 for 20000e Blue : Before tuning Red : After tuning

# Pixels ToT

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Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System - PCIe

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  • 2. FE-I4 Readout system using PCI Express

7 Series FPGAs Integrated Block for PCI Wishbone express core DMA Controller

TxCore RxCore Trigger Unit

RxBridge DDR3 Controller

Wishbone Bus DMA Wishbone Bus DDR3 Memory FE ASIC

Encoder & Serializer

Decoder & Deserializer

Send command & trigger Readout Data

PCI Express

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Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System - PCIe

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  • Direct Memory Access
  • PCI Express

READ ~ 750MB/s WRITE ~ 700MB/s

Data block size [KByte]

  • 2. FE-I4 Readout system using PCI Express

Program Memory PCI Express Memory

WRITE READ

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Kuno and Yamanaka Group Year-End Presentation 2017

5.Summary

  • FE-I4 Readout system on KC705 was developed !
  • High speed DAQ system


→ Transfer speed performance between FPGA and PC was achieved ! ~750MB/s (READ)


  • Future
  • Complete DAQ system


+ Understanding data transfer performance
 + Adapt to RD53A

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Additional Slides

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Kuno and Yamanaka Group Year-End Presentation 2017

Development components

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FPGA Firmware DAQ Software Signal transmission test

DAQ Group

Frontend ASIC Evaluation FPGA Board

Zynq DAQ System

Pixel Assembly Group

Characteristic test

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Kuno and Yamanaka Group Year-End Presentation 2017

2.HL-LHC ATLAS Pixel detector

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Digitization of signal & some functions Detect charged particles Semiconductor Sensor ASIC

(Application specific integrated circuit

Pixel detector in ATLAS

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Kuno and Yamanaka Group Year-End Presentation 2017

Hit rate & Data rate

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Kuno and Yamanaka Group Year-End Presentation 2017

5 Gbps / chip serial output

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  • Estimation of requirement 5 Gbps/chip
  • Hit occupancy / FE / event : ~200
  • Data frame length per 1 Hit : 26 bit
  • Trigger rate : 1 MHz

200 Hits/event × 26 bit/Hit × 1 MHz = ~5 Gbps (~650 MB/s)

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Kuno and Yamanaka Group Year-End Presentation 2017

Pixel Sensor readout ASIC prototype (RD53A)

  • ATLAS及びCMSのフェーズ２アップグレードに向けて開発されている


次世代読み出しASIC

  • デモンストレータ → 性能評価などが行われている
  • FPGAに実装可能なエミュレータが開発されている

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FE-I4 RD53A Cell Size 50x250 um2

50x50 um2 (25x100) um2)

Pixel Matrix 80x336

400x192

Chip Size 18.2x19.0 mm2

20.0x2.8 mm2

Transistor ~80 M

~ 1 G

Input Rate 40 Mbps

160 Mbps

Output Rate 160 Mbps

~5 Gbps

Trigger Rate 200 kHz

1 MHz (L0)

Radiation 300 Mrad

> 500 Mrad

CMOS Process 130 nm

65 nm

Thickness 150 um

150 um

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Kuno and Yamanaka Group Year-End Presentation 2017

Analog pixel schematic diagram

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ToT Tuning Threshold Tuning

Pixel threshold Global threshold

Charge Injection Q=C×Vcal

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Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System

thres_after_0 Entries 672 Mean 3596 RMS 60.61

Threshold [e] 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 # Pixels 20 40 60 80 100 120 140 160 180 200

thres_after_0 Entries 672 Mean 3596 RMS 60.61

Threshold [e] # Pixels

Target threshold : 3,600e

  • Operation Test - Threshold Tuning
  • Set Threshold for Hit judgment for each pixel
  • Adjust the feedback current for discriminator to tune target

threshold

  • Result was obtained by measurement.

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  • 1. FE-I4 Readout system using Ethernet

Hit occupancy PlsrDAC ~ Feedback Current

S-curve

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Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System

tot_after_0 Entries 672 Mean 10.02 RMS 0.5785

ToT 2 4 6 8 10 12 14 16 # Pixels 50 100 150 200 250

tot_after_0 Entries 672 Mean 10.02 RMS 0.5785

Target ToT : 10@20,000e

ToT # Pixels

  • Operation Test - ToT(Time over threshold) Tuning
  • ToT is determined with input charge amounts
  • Adjust the feedback current for preamp 


to tune target ToT.

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Threshold ∝Energy Time

ToT

  • 1. FE-I4 Readout system using Ethernet
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Kuno and Yamanaka Group Year-End Presentation 2017

4.ASIC Readout System - PCIe

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  • 2. FE-I4 Readout system using PCI Express

7 Series FPGAs Integrated Block for PCI Wishbone express core DMA Controller

TxCore RxCore Trigger Unit

RxBridge DDR3 Controller

Wishbone Bus DMA Wishbone Bus DDR3 Memory FE ASIC

Encoder & Serializer

Decoder & Deserializer

Send command & trigger Readout Data

PCI Express

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Kuno and Yamanaka Group Year-End Presentation 2017

DMA Operation time

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  • Operation Time of DMA transfer

  • btained by gettimeoday()


Left : Transfer time + Memory Allocation Time + a
 Right : Memory Allocation Time + a

Trials:100 Trials:100