Depth Lower Bound against Circuits with Sparse Orientation Sajin - - PowerPoint PPT Presentation

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Depth Lower Bound against Circuits with Sparse Orientation Sajin - - PowerPoint PPT Presentation

Depth Lower Bound against Circuits with Sparse Orientation Sajin Koroth 1 Jayalal Sarma 1 1 Algorithms and Complexity Theory Lab Department of Computer Science IIT Madras Chennai Theory Day, 2013 1 / 17 Circuit Model A circuit family C


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Depth Lower Bound against Circuits with Sparse Orientation

Sajin Koroth1 Jayalal Sarma1

1Algorithms and Complexity Theory Lab

Department of Computer Science IIT Madras

Chennai Theory Day, 2013

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Circuit Model

x1 x2 x3 x1 x2 x3 x4 C3 C4

A circuit family C computing a Boolean function f is such that for each n ∈ N, ∀x ∈ {0, 1}n f (x) = Cn(x), Cn ∈ C

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Circuit Model

x1 x2 x3 x1 x2 x3 x4 C3 C4

A circuit family C computing a Boolean function f is such that for each n ∈ N, ∀x ∈ {0, 1}n f (x) = Cn(x), Cn ∈ C A computation model which can compute any Boolean function.

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Circuit Model

x1 x2 x3 x1 x2 x3 x4 C3 C4

A circuit family C computing a Boolean function f is such that for each n ∈ N, ∀x ∈ {0, 1}n f (x) = Cn(x), Cn ∈ C A computation model which can compute any Boolean function. A circuit is a Direct Acyclic Graph

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Circuit Model

x1 x2 x3 x1 x2 x3 x4 C3 C4

A circuit family C computing a Boolean function f is such that for each n ∈ N, ∀x ∈ {0, 1}n f (x) = Cn(x), Cn ∈ C A computation model which can compute any Boolean function. A circuit is a Direct Acyclic Graph Important Parameters : Size : Number

  • f gates(internal nodes), Depth : The

longest path from root to any leaf.

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SLIDE 6

Circuit Model

x1 x2 x3 x1 x2 x3 x4 C3 C4

A circuit family C computing a Boolean function f is such that for each n ∈ N, ∀x ∈ {0, 1}n f (x) = Cn(x), Cn ∈ C A computation model which can compute any Boolean function. A circuit is a Direct Acyclic Graph Important Parameters : Size : Number

  • f gates(internal nodes), Depth : The

longest path from root to any leaf. Assumption : Internal gates are {∧, ∨, ¬} with fan-in {2, 2, 1}

  • respectively. (Bounded fan-in)

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Circuit Lower bounds - motivation

Nice combinatorial structure (graphs with additional information)

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Circuit Lower bounds - motivation

Nice combinatorial structure (graphs with additional information) Strong reasons to believe NP ⊂ PolySize∗ whereas P ⊂ PolySize. Hence NP ⊂ PolySize = ⇒ P = NP

∗If NP has polynomial size circuits then PH = Σ2 3 / 17

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SLIDE 9

Circuit Lower bounds - motivation

Nice combinatorial structure (graphs with additional information) Strong reasons to believe NP ⊂ PolySize∗ whereas P ⊂ PolySize. Hence NP ⊂ PolySize = ⇒ P = NP Depth captures “efficient” parallel computation.

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Circuit Lower bounds - motivation

Nice combinatorial structure (graphs with additional information) Strong reasons to believe NP ⊂ PolySize∗ whereas P ⊂ PolySize. Hence NP ⊂ PolySize = ⇒ P = NP Depth captures “efficient” parallel computation. Depth(Clique) ? = ω((log n)k) (NP vs NCk†) - does NP have efficient parallel algorithms ?

†NCk - poly-size, poly-log((log n)k) depth 3 / 17

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Restrictions on the model

Known circuit lower bounds against general circuits are very weak (5n size and 3 log n depth)

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Restrictions on the model

Known circuit lower bounds against general circuits are very weak (5n size and 3 log n depth) Strong lower bound against monotone circuits

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Restrictions on the model

Known circuit lower bounds against general circuits are very weak (5n size and 3 log n depth) Strong lower bound against monotone circuits A circuit is monotone iff it has no NOT(¬) gates.

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Restrictions on the model

Known circuit lower bounds against general circuits are very weak (5n size and 3 log n depth) Strong lower bound against monotone circuits A circuit is monotone iff it has no NOT(¬) gates. Monotone circuits computes monotone functions (and every monotone function is computed by a monotone circuit)

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Restrictions on the model

Known circuit lower bounds against general circuits are very weak (5n size and 3 log n depth) Strong lower bound against monotone circuits A circuit is monotone iff it has no NOT(¬) gates. Monotone circuits computes monotone functions (and every monotone function is computed by a monotone circuit) A function is monotone iff ∀x ≤ y, f (x) ≤ f (y)

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Restrictions on the model

Known circuit lower bounds against general circuits are very weak (5n size and 3 log n depth) Strong lower bound against monotone circuits A circuit is monotone iff it has no NOT(¬) gates. Monotone circuits computes monotone functions (and every monotone function is computed by a monotone circuit) A function is monotone iff ∀x ≤ y, f (x) ≤ f (y) A function is monotone iff changing bits from 0 to 1 in the input cannot decrease the function value.

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Monotone Depth lower bounds

Clique{n,n/2}(x)‡ where x is the undirected adjacency list of a graph is a monotone function, as adding edges cannot remove a clique. It is an NP-complete problem.

‡Clique{n,n/2}(x) = 1 iff Gx is an n-vertex graph containing a clique of size

n/2

§Ran Raz and Avi Wigderson. “Monotone circuits for matching require

linear depth”. In: J. ACM 39.3 (July 1992), pp. 736–744.

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Monotone Depth lower bounds

Clique{n,n/2}(x)‡ where x is the undirected adjacency list of a graph is a monotone function, as adding edges cannot remove a clique. It is an NP-complete problem. Raz and Wigderson : Perfect matching and Clique§ requires Ω(n) depth

‡Clique{n,n/2}(x) = 1 iff Gx is an n-vertex graph containing a clique of size

n/2

§Ran Raz and Avi Wigderson. “Monotone circuits for matching require

linear depth”. In: J. ACM 39.3 (July 1992), pp. 736–744.

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 1 x=01 y=11 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=01 Bob y=11 6 / 17

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 1 x=01 y=11 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=01 Bob y=11 A x1=0 6 / 17

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 x=01 y=11 1 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=01 Bob y=11 A x1=0 B 1 6 / 17

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 x=01 y=11 1 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=10 Bob y=11 A x1=0 B 1 x1=1 B 2 6 / 17

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 x=01 y=11 1 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=10 Bob y=00 A x1=0 B 1 x1=1 B 2 6 / 17

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 x=01 y=11 1 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=10 Bob y=00 A x1=0 B 1 x1=1 B 2 1 6 / 17

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 x=01 y=11 1 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=01 Bob y=00 A x1=0 B 1 x1=1 B 2 1 6 / 17

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Karchmer Wigderson Game

2 bit Parity Circuit Alice Bob 1 x=01 y=11 1 1 1

Aim

Alice is given x ∈ f −(1) and Bob is given y ∈ f −(0), goal is to find i ∈ [n] such that xi = yi

2 bit Parity KW protocol

  • 1. Send x1
  • 2. If x1 != y1 output 1 and stop, else send y2
  • 3. Output 2

Alice x=01 Bob y=00 A x1=0 B 1 x1=1 B 2 1 2 6 / 17

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Monotone KW-game (KW+(f ))

KW+(f )

Alice is given x ∈ f −1(1) and Bob is given y ∈ f −1(0) for a monotone function f . Goal : Find i ∈ [n] such that xi = 1 and yi = 0.

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Monotone KW-game (KW+(f ))

KW+(f )

Alice is given x ∈ f −1(1) and Bob is given y ∈ f −1(0) for a monotone function f . Goal : Find i ∈ [n] such that xi = 1 and yi = 0.

KW+(f ) = MDepth(f )

For every d-length protocol solving KW+(f ) there is a corresponding d-depth monotone circuit computing f and vice versa.

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Generalizing Monotone Lower bounds

Raz and Wigderson : KW+(f ) for Perfect matching and Clique¶ is Ω(n).

¶Ran Raz and Avi Wigderson. “Monotone circuits for matching require

linear depth”. In: J. ACM 39.3 (July 1992), pp. 736–744.

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Generalizing Monotone Lower bounds

Raz and Wigderson : KW+(f ) for Perfect matching and Clique is Ω(n). Their technique does not work to show similar lower bounds for KW(f ).

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SLIDE 31

Generalizing Monotone Lower bounds

Raz and Wigderson : KW+(f ) for Perfect matching and Clique is Ω(n). Their technique does not work to show similar lower bounds for KW(f ). To go beyond monotone : controlled non-monotonicity

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Generalizing Monotone Lower bounds

Raz and Wigderson : KW+(f ) for Perfect matching and Clique is Ω(n). Their technique does not work to show similar lower bounds for KW(f ). To go beyond monotone : controlled non-monotonicity Limiting negations : Amano and Maruoka¶ proved that Clique requires super polynomial size even 1

6 log log n negations are allowed.

¶Kazuyuki Amano and Akira Maruoka. “A superpolynomial lower bound for

a circuit computing the clique function with at most (1/6) log log n negation gates”. In: SIAM Journal on Computing 35.1 (2005), pp. 201–216.

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Generalizing Monotone Lower bounds

Raz and Wigderson : KW+(f ) for Perfect matching and Clique is Ω(n). Their technique does not work to show similar lower bounds for KW(f ). To go beyond monotone : controlled non-monotonicity Limiting negations : Amano and Maruoka proved that Clique requires super polynomial size even 1

6 log log n negations are allowed.

A contrasting picture : Fischer¶ proved that lower bounds against log n is sufficient.

¶Michael Fischer. “The complexity of negation-limited networks A brief

survey”. In: Automata Theory and Formal Languages 2nd GI Conference Kaiserslautern, May 2023, 1975. Vol. 33. Lecture Notes in Computer Science. Springer Berlin / Heidelberg, 1975, pp. 71–82.

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SLIDE 34

Generalizing Monotone Lower bounds

Raz and Wigderson : KW+(f ) for Perfect matching and Clique is Ω(n). Their technique does not work to show similar lower bounds for KW(f ). To go beyond monotone : controlled non-monotonicity Limiting negations : Amano and Maruoka proved that Clique requires super polynomial size even 1

6 log log n negations are allowed.

A contrasting picture : Fischer proved that lower bounds against log n is sufficient. Amano and Maruoka’s size lower bound against bounded fan-in circuits implies a depth lower bound of (log n)

√log n against circuits

with 1

6 log log n negations.

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Generalizing Monotone Lower bounds

Raz and Wigderson : KW+(f ) for Perfect matching and Clique is Ω(n). Their technique does not work to show similar lower bounds for KW(f ). To go beyond monotone : controlled non-monotonicity Limiting negations : Amano and Maruoka proved that Clique requires super polynomial size even 1

6 log log n negations are allowed.

A contrasting picture : Fischer proved that lower bounds against log n is sufficient. Amano and Maruoka’s size lower bound against bounded fan-in circuits implies a depth lower bound of (log n)

√log n against circuits

with 1

6 log log n negations.

Our restriction generalizes KW+(f ). And it does not go through size lower bounds.

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Orientation

Monotone circuits are also circuits such that sub-circuit rooted at any gate computes a monotone function.

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Orientation

Monotone circuits are also circuits such that sub-circuit rooted at any gate computes a monotone function. Restriction (high-level idea) : Circuits where every internal gate computes a function which is not “far” from monotone.

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Orientation

Monotone circuits are also circuits such that sub-circuit rooted at any gate computes a monotone function. Restriction (high-level idea) : Circuits where every internal gate computes a function which is not “far” from monotone. Main Result (high-level view) : A trade-off between “far”-ness and circuit depth.

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Orientation : Definition

Consider a function f : {0, 1}n → {0, 1}.

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Orientation : Definition

Consider a function f : {0, 1}n → {0, 1}. Let C be the circuit computing f with minimum number of “leaf” negations (no internal negations allowed), say k.

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Orientation : Definition

Consider a function f : {0, 1}n → {0, 1}. Let C be the circuit computing f with minimum number of “leaf” negations (no internal negations allowed), say k. Orientation of f is then defined to be set of k input variables in C which are negated. And the weight of the orientation of f is defined to be k.

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Orientation : Definition

Consider a function f : {0, 1}n → {0, 1}. Let C be the circuit computing f with minimum number of “leaf” negations (no internal negations allowed), say k. Orientation of f is then defined to be set of k input variables in C which are negated. And the weight of the orientation of f is defined to be k. Orientation of a function f : {0, 1}n → {0, 1} is a β ∈ {0, 1}n such that there is a monotone function h : {0, 1}2n → {0, 1} with ∀x, f (x) = h(x, x ⊕ β).

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Main Theorem

Weight of Orientation of a Circuit

A circuit C is weight w-restricted if at each gate g the sub-circuit rooted at that gate computes a function fg whose weight of orientation is at most w.

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Main Theorem

Weight of Orientation of a Circuit

A circuit C is weight w-restricted if at each gate g the sub-circuit rooted at that gate computes a function fg whose weight of orientation is at most w.

Lower bound by weight restriction

Let C be a weight w-restricted circuit computing a monotone function f : {0, 1}n → {0, 1}, then Depth(C) = Ω KW+(f ) 4w + 1

  • 11 / 17
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Corollary

For Clique{n, n

2}, KW+(f ) = Ω(n) 12 / 17

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Corollary

For Clique{n, n

2}, KW+(f ) = Ω(n)

By our theorem, for w =

n (log n)1+ǫ ,

Depth(C) = Ω

  • KW+(f )

3w+1

  • = Ω(

n

n (log n)1+ǫ ) = Ω((log n)1+ǫ) 12 / 17

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Corollary

For Clique{n, n

2}, KW+(f ) = Ω(n)

By our theorem, for w =

n (log n)1+ǫ ,

Depth(C) = Ω

  • KW+(f )

3w+1

  • = Ω(

n

n (log n)1+ǫ ) = Ω((log n)1+ǫ)

NP = NC1[w <

√m (log m)1+ǫ]

NP does not have log-depth circuits if only sub-functions of weight

√m (log m)1+ǫ are allowed to be computed by the circuit where m is the input

size.

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Corollary

For Clique{n, n

2}, KW+(f ) = Ω(n)

By our theorem, for w =

n (log n)1+ǫ ,

Depth(C) = Ω

  • KW+(f )

3w+1

  • = Ω(

n

n (log n)1+ǫ ) = Ω((log n)1+ǫ)

Weight |input| is sufficient to compute any function. For Clique{n,n/2}, |input| = n

2

  • .

NP = NC1[w <

√m (log m)1+ǫ]

NP does not have log-depth circuits if only sub-functions of weight

√m (log m)1+ǫ are allowed to be computed by the circuit where m is the input

size.

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Proof Sketch

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Proof Sketch

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Proof Sketch

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Proof Sketch

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Proof Sketch

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Proof Sketch

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Proof Sketch

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Proof Sketch

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Proof Sketch

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Proof Sketch

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SLIDE 59

Proof Sketch - Handling negations

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Proof Sketch - Handling negations

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Proof Sketch - Handling negations

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Proof Sketch - Handling negations

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Proof Sketch - Handling negations

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Proof Sketch - Handling negations

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Proof Sketch - Handling negations

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A barrier and connection to negations

Can we handle higher weight β’s if we restrict the number of gates whose orientation is non-zero ?

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A barrier and connection to negations

Can we handle higher weight β’s if we restrict the number of gates whose orientation is non-zero ?

  • No. There exists a monotone function f which is not computed by

sub-linear depth monotone circuits, but it is a computed by a O(log2 n) depth circuit having only two gates with non-zero

  • rientation.

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SLIDE 68

A barrier and connection to negations

Can we handle higher weight β’s if we restrict the number of gates whose orientation is non-zero ?

  • No. There exists a monotone function f which is not computed by

sub-linear depth monotone circuits, but it is a computed by a O(log2 n) depth circuit having only two gates with non-zero

  • rientation.

If you have t negations in a size s circuit how many non-zero

  • rientation gates are there ?

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SLIDE 69

A barrier and connection to negations

Can we handle higher weight β’s if we restrict the number of gates whose orientation is non-zero ?

  • No. There exists a monotone function f which is not computed by

sub-linear depth monotone circuits, but it is a computed by a O(log2 n) depth circuit having only two gates with non-zero

  • rientation.

If you have t negations in a size s circuit how many non-zero

  • rientation gates are there ?

The circuit can be transformed to another computing the same function of size 2t(s + 2t) + 2t having at most 2t−1(t + 2) − 1 internal gates of non-zero orientation.

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Uniform orientation

A circuit is said to be of uniform orientation for a specific β if all the sub-functions computed by the circuit can be computed using negated variables indexed by β.

¶Ran Raz and Avi Wigderson. “Probabilistic Communication Complexity of

Boolean Relations”. In: Proc. of the 30th FOCS. 1989, pp. 562–567.

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SLIDE 71

Uniform orientation

A circuit is said to be of uniform orientation for a specific β if all the sub-functions computed by the circuit can be computed using negated variables indexed by β. Uniform orientation of weight w is equivalent to w leaf negations

¶Ran Raz and Avi Wigderson. “Probabilistic Communication Complexity of

Boolean Relations”. In: Proc. of the 30th FOCS. 1989, pp. 562–567.

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SLIDE 72

Uniform orientation

A circuit is said to be of uniform orientation for a specific β if all the sub-functions computed by the circuit can be computed using negated variables indexed by β. Uniform orientation of weight w is equivalent to w leaf negations Raz and Wigderson¶ proved that any NC1 circuit computing st-connectivity requires Ω(n2) leaf negations.

¶Ran Raz and Avi Wigderson. “Probabilistic Communication Complexity of

Boolean Relations”. In: Proc. of the 30th FOCS. 1989, pp. 562–567.

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SLIDE 73

Uniform orientation

A circuit is said to be of uniform orientation for a specific β if all the sub-functions computed by the circuit can be computed using negated variables indexed by β. Uniform orientation of weight w is equivalent to w leaf negations Raz and Wigderson¶ proved that any NC1 circuit computing st-connectivity requires Ω(n2) leaf negations. We prove that for any circuit C computing Clique if the orientation β ∈ {0, 1}n of the circuit is such that there is subset of vertices U and ǫ > 0 such that |U| ≥ logk+ǫ n for which βe = 0 for all edges e within U, then C must have depth ω(logk n).

¶Ran Raz and Avi Wigderson. “Probabilistic Communication Complexity of

Boolean Relations”. In: Proc. of the 30th FOCS. 1989, pp. 562–567.

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SLIDE 74

Uniform orientation

A circuit is said to be of uniform orientation for a specific β if all the sub-functions computed by the circuit can be computed using negated variables indexed by β. Uniform orientation of weight w is equivalent to w leaf negations Raz and Wigderson¶ proved that any NC1 circuit computing st-connectivity requires Ω(n2) leaf negations. We prove that for any circuit C computing Clique if the orientation β ∈ {0, 1}n of the circuit is such that there is subset of vertices U and ǫ > 0 such that |U| ≥ logk+ǫ n for which βe = 0 for all edges e within U, then C must have depth ω(logk n). A contrasting picture : Any circuit C computing Clique with depth d has an equivalent circuit C

′ of depth d + c log n with an orientation

β such that there are c log n vertices U with none of the edges e(u, v), u, v ∈ U which has βe(u,v) = 1.

¶Ran Raz and Avi Wigderson. “Probabilistic Communication Complexity of

Boolean Relations”. In: Proc. of the 30th FOCS. 1989, pp. 562–567.

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SLIDE 75

Thank You

Q

Questions ?

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