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Upper and Lower Loop Bound Estimation by Symbolic Execution and Loop Acceleration
Pavel ˇ Cadek1
1TU Wien, Austria
Upper and Lower Loop Bound Estimation by Symbolic Execution and Loop - - PowerPoint PPT Presentation
Upper and Lower Loop Bound Estimation by Symbolic Execution and Loop Acceleration Pavel Cadek 1 1 TU Wien, Austria Formal Methods in Computer-Aided Design 30 Oct - 2 Nov, 2018 Loop Bound Analysis Upper loop bound: max { n , 0 } Lower loop
1TU Wien, Austria
Pavel ˇ Cadek ( TU Wien, Austria ) FMCAD 2018 2 / 5
Pavel ˇ Cadek ( TU Wien, Austria ) FMCAD 2018 3 / 5
Pavel ˇ Cadek ( TU Wien, Austria ) FMCAD 2018 4 / 5
Pavel ˇ Cadek ( TU Wien, Austria ) FMCAD 2018 5 / 5