Dependent Types -Ware: Hardware Description with Next steps Dive - - PowerPoint PPT Presentation

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 1

Π-Ware: Hardware Description with Dependent Types

João Paulo Pizani Flor, B.Sc

<j.p.pizaniflor@students.uu.nl>

• dr. W. S. Swierstra

<w.s.swierstra@uu.nl>

Department of Information and Computing Sciences Utrecht University

Saturday 12th July, 2014

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 2

Table of Contents

Intro Quick intro Context Inspired by Dive into Π-Ware Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists Current / next steps Current work Next steps

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 3

Section 1 Intro

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 4

One-sentence definition

Π-Ware is a Domain-Specific Language (DSL) embedded in Agda for modeling hardware, synthesizing it and reasoning about its properties.

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 5

Hardware Design

Hardware design is a complex and “booming” activity:

▶ Algorithms increasingly benefit from hardware acceleration

• Moore’s Law still holds
• Microarchitecture optimization has diminishing returns

▶ Hardware development has stricter requirements

• Mistakes found in “production” are much more serious
• Thus the need for extensive validation/verification
• Can encompass up to 50% of total development costs

▶ Need to combine productivity/ease-of-use with rigor

• Detect mistakes early

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 6

Hardware design

Functional programming has already been used to help hardware design (since the 1980s).

▶ First, independent DSLs (e.g. muFP) ▶ Then, as embedded DSLs

• Prominently, in Haskell

▶ Question: How to use DTP to benefit hardware design?

• Experimenting by embedding in a DTP language
• Namely, Π-Ware is embedded in Agda (ITT, Martin-Löf)

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 7

Some features of Agda important for us

Not exclusively…

▶ Dependent inductive families

• Circuits are indexed by the sizes/types of their ports

▶ Dependent pattern matching ▶ “Dependent type classes”

• Dependent records + instance arguments

▶ Coinductive types / proofs

• When modeling / proving sequential behaviour

▶ Parameterized modules

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 8

Credit where credit is due

▶ Lava – Haskell (Chalmers)

• Pragmatic, easy-to-use, popular

▶ ForSyDe – Haskell (KTH)

• Hierarchical synthesis
• Static size checking

▶ Coquet – Coq (INRIA)

• Main influence
• Reasoning about circuit behaviour with Coq’s tactics
• Models circuits with structural combinators

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 9

Section 2 Dive into Π-Ware

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 10

Modeling circuits

▶ Deep-embedded – explicit circuit inductive family: ℂ′ ▶ Descriptions are at gate level and architectural

• Fundamental constructors: 𝖮𝗃𝗆, 𝖧𝖻𝗎𝖿 (parameterized)
• Constructors for structural combination

𝖾𝖻𝗎𝖻 ℂ′ ∶ ℕ → ℕ → 𝖳𝖿𝗎 𝖾𝖻𝗎𝖻 ℂ′ 𝗑𝗂𝖿𝗌𝖿 𝖮𝗃𝗆 ∶ ℂ′ 𝗔𝖿𝗌𝗉 𝗔𝖿𝗌𝗉 𝖧𝖻𝗎𝖿 ∶ (𝑕# ∶ 𝖧𝖻𝗎𝖿𝗍#) → ℂ′ (𝗃𝗈𝗍 𝑕#) (𝗉𝗏𝗎𝗍 𝑕#) 𝖰𝗆𝗏𝗁 ∶ {𝑗 𝑝 ∶ ℕ} → (𝑔 ∶ 𝖦𝗃𝗈 𝑝 → 𝖦𝗃𝗈 𝑗) → ℂ′ 𝑗 𝑝

_⟫′_ ∶ {𝑗 𝑛 𝑝 ∶ ℕ} → ℂ′ 𝑗 𝑛 → ℂ′ 𝑛 𝑝 → ℂ′ 𝑗 𝑝 _|′_ ∶ {𝑗1 𝑝1 𝑗2 𝑝2 ∶ ℕ} → ℂ′ 𝑗1 𝑝1 → ℂ′ 𝑗2 𝑝2 → ℂ′ (𝑗1 + 𝑗2) (𝑝1 + 𝑝2) _| +′ _ ∶ {𝑗1 𝑗2 𝑝 ∶ ℕ} → ℂ′ 𝑗1 𝑝 → ℂ′ 𝑗2 𝑝 → ℂ′ (𝗍𝗏𝖽 (𝑗1 ⊔ 𝑗2)) 𝑝

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 11

Sequential circuits

▶ Built using 𝖤𝖿𝗆𝖻𝗓𝖬𝗉𝗉𝗊, introduces state (latch)

𝖤𝖿𝗆𝖻𝗓𝖬𝗉𝗉𝗊 ∶ {𝑗 𝑝 𝑚 ∶ ℕ} (𝑑 ∶ ℂ′ (𝑗 + 𝑚) (𝑝 + 𝑚)) {𝑞 ∶ 𝖽𝗉𝗇𝖼′ 𝑑} → ℂ′ 𝑗 𝑝

▶ Avoid evaluating combinational loops by carrying a proof

𝖽𝗉𝗇𝖼′ ∶ {𝑗 𝑝 ∶ ℕ} → ℂ′ 𝑗 𝑝 → 𝖳𝖿𝗎 𝖽𝗉𝗇𝖼′ 𝖮𝗃𝗆 = ⊤ 𝖽𝗉𝗇𝖼′ (𝖧𝖻𝗎𝖿 _) = ⊤ 𝖽𝗉𝗇𝖼′ (𝖰𝗆𝗏𝗁 _) = ⊤ 𝖽𝗉𝗇𝖼′ (𝖤𝖿𝗆𝖻𝗓𝖬𝗉𝗉𝗊 _) = ⊥ 𝖽𝗉𝗇𝖼′ (𝑑1 ⟫′ 𝑑2) = 𝖽𝗉𝗇𝖼′ 𝑑1 × 𝖽𝗉𝗇𝖼′ 𝑑2

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 12

Abstraction (𝖡𝗎𝗉𝗇𝗃𝖽)

▶ Circuits operate over words, which are made of 𝖡𝗎𝗉𝗇

• PiWare “ships” with 𝖢𝗉𝗉𝗆 atoms
• Another example: IEEE1164 multi-valued (std_logic)

𝗌𝖿𝖽𝗉𝗌𝖾 𝖡𝗎𝗉𝗇𝗃𝖽 ∶ 𝖳𝖿𝗎𝟤 𝗑𝗂𝖿𝗌𝖿 𝗀𝗃𝖿𝗆𝖾 𝖡𝗎𝗉𝗇 ∶ 𝖳𝖿𝗎 |𝖡𝗎𝗉𝗇| − 𝟤 ∶ ℕ 𝗈 → 𝖻𝗎𝗉𝗇 ∶ 𝖦𝗃𝗈 (𝗍𝗏𝖽 |𝐵𝑢𝑝𝑛| − 1) → 𝐵𝑢𝑝𝑛 𝖻𝗎𝗉𝗇 → 𝗈 ∶ 𝐵𝑢𝑝𝑛 → 𝖦𝗃𝗈 (𝗍𝗏𝖽 |𝐵𝑢𝑝𝑛| − 1) 𝗃𝗈𝗐 − 𝗆𝖿𝗀𝗎 ∶ ∀ 𝑗 → 𝑏𝑢𝑝𝑛 → 𝑜 (𝑜 → 𝑏𝑢𝑝𝑛 𝑗) ≡ 𝑗 𝗃𝗈𝗐 − 𝗌𝗃𝗁𝗂𝗎 ∶ ∀ 𝑏 → 𝑜 → 𝑏𝑢𝑝𝑛 (𝑏𝑢𝑝𝑛 → 𝑜 𝑏) ≡ 𝑏

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 13

Computation abstraction (𝖧𝖻𝗎𝖿𝗍)

▶ Circuits parameterized by a record of “fundamental” 𝖧𝖻𝗎𝖿𝗍

• Specifying each gate’s interface (input/output sizes)
• And its semantics (as a function over words)

𝗌𝖿𝖽𝗉𝗌𝖾 𝖧𝖻𝗎𝖿𝗍 ∶ 𝖳𝖿𝗎 𝗑𝗂𝖿𝗌𝖿 𝗀𝗃𝖿𝗆𝖾 |𝖧𝖻𝗎𝖿𝗍| − 𝟤 ∶ ℕ 𝗃𝗈𝗍 𝗉𝗏𝗎𝗍 ∶ 𝖦𝗃𝗈 (𝗍𝗏𝖽 |𝐻𝑏𝑢𝑓𝑡| − 1) → ℕ 𝗍𝗊𝖿𝖽 ∶ (𝑕 ∶ 𝖦𝗃𝗈 (𝗍𝗏𝖽 |𝐻𝑏𝑢𝑓𝑡| − 1)) → (𝖷 (𝑗𝑜𝑡 𝑕) → 𝖷 (𝑝𝑣𝑢𝑡 𝑕)) |𝖧𝖻𝗎𝖿𝗍| = 𝗍𝗏𝖽 |𝖧𝖻𝗎𝖿𝗍| − 𝟤 𝖧𝖻𝗎𝖿𝗍# = 𝖦𝗃𝗈 |𝖧𝖻𝗎𝖿𝗍|

▶ “Black box” for semantics / reasoning

• Correctness assumed

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 14

Data abstraction (input/output)

▶ The “core” circuit type (ℂ′) is indexed by sizes (ℕ)

• Has words of the respective sizes as inputs and outputs

▶ The high level type (ℂ) is indexed by meta (Agda) types

• Specifically, finite types

𝖾𝖻𝗎𝖻 ℂ (𝛽 𝛾 ∶ 𝖳𝖿𝗎) {𝑗 𝑘 ∶ ℕ} ∶ 𝖳𝖿𝗎 𝗑𝗂𝖿𝗌𝖿 𝖭𝗅ℂ ∶ ⦃ 𝑡𝛽 ∶ ⇓ 𝖷 ⇑ 𝛽 {𝑗} ⦄ ⦃ 𝑡𝛾 ∶ ⇓ 𝖷 ⇑ 𝛾 {𝑘} ⦄ → ℂ′ 𝑗 𝑘 → ℂ 𝛽 𝛾 {𝑗} {𝑘} 𝖽𝗉𝗇𝖼 ∶ ∀ {𝛽 𝑗 𝛾 𝑘} → ℂ 𝛽 𝛾 {𝑗} {𝑘} → 𝖳𝖿𝗎 𝖽𝗉𝗇𝖼 (𝖭𝗅ℂ 𝑑′) = 𝖽𝗉𝗇𝖼′ 𝑑′

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 15

Data abstraction (𝖳𝗓𝗈𝗎𝗂𝖿𝗍𝗃𝗔𝖻𝖼𝗆𝖿)

▶ We define a class of finite types

• Practically, they are types which can be mapped to words
• The isomorphism resides in the 𝖳𝗓𝗈𝗎𝗂𝖿𝗍𝗃𝗔𝖻𝖼𝗆𝖿 type class

𝖷 ∶ ℕ → 𝖳𝖿𝗎 𝖷 = 𝖶𝖿𝖽 𝖡𝗎𝗉𝗇 𝗌𝖿𝖽𝗉𝗌𝖾 ⇓ 𝖷 ⇑ (𝛽 ∶ 𝖳𝖿𝗎) {𝑗 ∶ ℕ} ∶ 𝖳𝖿𝗎 𝗑𝗂𝖿𝗌𝖿 𝖽𝗉𝗈𝗍𝗎𝗌𝗏𝖽𝗎𝗉𝗌 ⇓ 𝖷 ⇑ [_,_] 𝗀𝗃𝖿𝗆𝖾 ⇓ ∶ 𝛽 → 𝖷 𝑗 ⇑ ∶ 𝖷 𝑗 → 𝛽

▶ Instances for _ × _, _ ⊎ _, 𝖶𝖿𝖽, 𝖢𝗉𝗉𝗆

• Lack recursive instance search

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 16

Simulation semantics

▶ “Purely combinational” vs. sequential ▶ Simulation functions in 2 levels of abstraction

• Low-level eval: ℂ′ 𝑗 𝑝 → (𝖷 𝑗 → 𝖷 𝑝)
• High-level eval: ℂ 𝛽 𝛾 → (𝛽 → 𝛾)

⟦_⟧′ ∶ {𝑗 𝑝 ∶ ℕ} → (𝑑 ∶ ℂ′ 𝑗 𝑝) {𝑞 ∶ 𝖽𝗉𝗇𝖼′ 𝑑} → (𝖷 𝑗 → 𝖷 𝑝) ⟦ 𝖮𝗃𝗆 ⟧′ = 𝖽𝗉𝗈𝗍𝗎 𝜁 ⟦ 𝖧𝖻𝗎𝖿 𝑕# ⟧′ = 𝗍𝗊𝖿𝖽 𝑕# ⟦ 𝖰𝗆𝗏𝗁 𝑞 ⟧′ = 𝗊𝗆𝗏𝗁𝖯𝗏𝗎𝗊𝗏𝗎𝗍 𝑞 ⟦ 𝑑1 ⟫′ 𝑑2 ⟧′ {𝑞1 , 𝑞2} = ⟦ 𝑑2 ⟧′ {𝑞2} ∘ ⟦ 𝑑1 ⟧′ {𝑞1} ⟦ _|′_ {𝑗1} 𝑑1 𝑑2 ⟧′ {𝑞1 , 𝑞2} = 𝗏𝗈𝖽𝗏𝗌𝗌𝗓′ _ + +_ ∘ 𝗇𝖻𝗊 (⟦ 𝑑1 ⟧′ {𝑞1}) (⟦ 𝑑2 ⟧′ {𝑞2}) ∘ 𝗍𝗊𝗆𝗃𝗎𝖡𝗎′ 𝑗1 ⟦ _| +′ _ {𝑗1} 𝑑1 𝑑2 ⟧′ {𝑞1 , 𝑞2} = [ ⟦ 𝑑1 ⟧′ {𝑞1} , ⟦ 𝑑2 ⟧′ {𝑞2} ]′ ∘ 𝗏𝗈𝗎𝖻𝗁 {𝑗1} ⟦ 𝖤𝖿𝗆𝖻𝗓𝖬𝗉𝗉𝗊 𝑑 ⟧′ {()} 𝑤

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 17

Simulation semantics

▶ “High-level” simulation has a pretty simple definition

⟦_⟧ ∶ ∀ {𝛽 𝑗 𝛾 𝑘} → (𝑑 ∶ ℂ 𝛽 𝛾 {𝑗} {𝑘}) {𝑞 ∶ 𝖽𝗉𝗇𝖼 𝑑} → (𝛽 → 𝛾) ⟦_⟧ (𝖭𝗅ℂ ⦃ 𝑡𝛽 ⦄ ⦃ 𝑡𝛾 ⦄ 𝑑′) = ⇑ ∘ ⟦ 𝑑′ ⟧′ ∘ ⇓ ⟦_⟧∗ ∶ ∀ {𝛽 𝑗 𝛾 𝑘} → ℂ 𝛽 𝛾 {𝑗} {𝑘} → (𝖳𝗎𝗌𝖿𝖻𝗇 𝛽 → 𝖳𝗎𝗌𝖿𝖻𝗇 𝛾) ⟦_⟧∗ (𝖭𝗅ℂ ⦃ 𝑡𝛽 ⦄ ⦃ 𝑡𝛾 ⦄ 𝑑′) = 𝗇𝖻𝗊 ⇑ ∘ ⟦ 𝑑′ ⟧∗′ ∘ 𝗇𝖻𝗊 ⇓

▶ Let’s go over sequential simulation in a bit more detail…

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 18

Sequential simulation

▶ Modeled using causal stream functions (Uustalu, 2006)

• Output depends on current and previous inputs, not future
• Implemented in Agda as non-empty lists (𝖬𝗃𝗍𝗎+)

⟦_⟧ ∶ {𝑗 𝑝 ∶ ℕ} → ℂ′ 𝑗 𝑝 → (𝖷 𝑗 ⇒ 𝖷 𝑝) ⟦ 𝖮𝗃𝗆 ⟧ (𝑥0 , _) = ⟦ 𝖮𝗃𝗆 ⟧′ 𝑥0 ⟦ 𝖧𝖻𝗎𝖿 𝑕# ⟧ (𝑥0 , _) = ⟦ 𝖧𝖻𝗎𝖿 𝑕# ⟧′ 𝑥0 ⟦ 𝖰𝗆𝗏𝗁 𝑞 ⟧ (𝑥0 , _) = 𝗊𝗆𝗏𝗁𝖯𝗏𝗎𝗊𝗏𝗎𝗍 𝑞 𝑥0 ⟦ 𝖤𝖿𝗆𝖻𝗓𝖬𝗉𝗉𝗊 {𝗉 = 𝑘} 𝑑 ⟧ = 𝗎𝖻𝗅𝖿𝗐 𝑘 ∘ 𝖾𝖿𝗆𝖻𝗓 {𝗉 = 𝑘} 𝑑 ⟦ 𝑑1 ⟫′ 𝑑2 ⟧ = ⟦ 𝑑2 ⟧ ∘ 𝗇𝖻𝗊+ ⟦ 𝑑1 ⟧ ∘ 𝗎𝖻𝗃𝗆𝗍+ ⟦ _|′_ {𝑗1} 𝑑1 𝑑2 ⟧ = 𝗏𝗈𝖽𝗏𝗌𝗌𝗓′ _ + +_ ∘ 𝗇𝖻𝗊 ⟦ 𝑑1 ⟧ ⟦ 𝑑2 ⟧ ∘ 𝗏𝗈𝗔𝗃𝗊+ ∘ 𝗍𝗊𝗆𝗃𝗎𝖡𝗎+ 𝑗1 ⟦ _| +′ _ {𝑗1} 𝑑1 𝑑2 ⟧ (𝑥0 , 𝑥−) 𝗑𝗃𝗎𝗂 𝗏𝗈𝗎𝖻𝗁 {𝑗1} 𝑥0 | 𝗏𝗈𝗎𝖻𝗁𝖬𝗃𝗍𝗎 {𝑗1} 𝑥− ... | 𝗃𝗈𝗄𝟤 𝑥0

1 | 𝑥− 1 , _

= ⟦ 𝑑1 ⟧ (𝑥0

1 , 𝑥− 1 )

... | 𝗃𝗈𝗄𝟥 𝑥0

2 | _

, 𝑥−

2 = ⟦ 𝑑2 ⟧ (𝑥0 2 , 𝑥− 2 )

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 19

Sequential simulation

▶ We “run” the causal eval to get a 𝖳𝗎𝗌𝖿𝖻𝗇 based eval

Γ ∶ (𝛽 ∶ 𝖳𝖿𝗎) → 𝖳𝖿𝗎 Γ = 𝖬𝗃𝗍𝗎+

_ ⇒ _ ∶ (𝛽 𝛾 ∶ 𝖳𝖿𝗎) → 𝖳𝖿𝗎

𝛽 ⇒ 𝛾 = Γ 𝛽 → 𝛾 𝗌𝗏𝗈 ∶ ∀ {𝛽 𝛾} → (𝛽 ⇒ 𝛾) → (𝖳𝗎𝗌𝖿𝖻𝗇 𝛽 → 𝖳𝗎𝗌𝖿𝖻𝗇 𝛾) 𝗌𝗏𝗈 𝑔 (𝑦0 ∷ 𝑦+) = 𝗌𝗏𝗈′ 𝑔 ((𝑦0 , []) , ♭ 𝑦+) 𝗑𝗂𝖿𝗌𝖿 𝗌𝗏𝗈′ ∶ ∀ {𝛽 𝛾} → (𝛽 ⇒ 𝛾) → (Γ 𝛽 × 𝖳𝗎𝗌𝖿𝖻𝗇 𝛽) → 𝖳𝗎𝗌𝖿𝖻𝗇 𝛾 𝗌𝗏𝗈′ 𝑔 ((𝑦0 , 𝑦−) , (𝑦1 ∷ 𝑦+)) = 𝑔 (𝑦0 , 𝑦−) ∷ ♯ 𝗌𝗏𝗈′ 𝑔 ((𝑦1 , 𝑦0 ∷ 𝑦−) , ♭ 𝑦+) ⟦_⟧∗′ ∶ {𝑗 𝑝 ∶ ℕ} → ℂ′ 𝑗 𝑝 → (𝖳𝗎𝗌𝖿𝖻𝗇 (𝖷 𝑗) → 𝖳𝗎𝗌𝖿𝖻𝗇 (𝖷 𝑝)) ⟦_⟧∗′ = 𝗌𝗏𝗈 ∘ ⟦_⟧

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 20

Reasoning about circuit properties

▶ Use ⟦_⟧ and ⟦_⟧∗ to express circuit behaviour ▶ Functional correctness: equality with some specification

• Also depends on the 𝖳𝗓𝗈𝗎𝗂𝖿𝗍𝗃𝗔𝖻𝖼𝗆𝖿 instances
• Could benefit from proof automation (case analysis, etc.)
• Investigating “proof combinators”

𝗊𝗌𝗉𝗉𝗀𝖦𝖻𝖾𝖾𝖢𝗉𝗉𝗆 ∶ ∀ 𝑏 𝑐 𝑑 → ⟦ 𝗀𝖻𝖾𝖾 ⟧ ((𝑏 , 𝑐) , 𝑑) ≡ 𝗀𝖻𝖾𝖾𝖳𝗊𝖿𝖽 𝑏 𝑐 𝑑 𝗊𝗌𝗉𝗉𝗀𝖦𝖻𝖾𝖾𝖢𝗉𝗉𝗆 𝗎𝗌𝗏𝖿 𝗎𝗌𝗏𝖿 𝗎𝗌𝗏𝖿 = 𝗌𝖿𝗀𝗆 𝗊𝗌𝗉𝗉𝗀𝖦𝖻𝖾𝖾𝖢𝗉𝗉𝗆 𝗎𝗌𝗏𝖿 𝗎𝗌𝗏𝖿 𝗀𝖻𝗆𝗍𝖿 = 𝗌𝖿𝗀𝗆 𝗊𝗌𝗉𝗉𝗀𝖦𝖻𝖾𝖾𝖢𝗉𝗉𝗆 𝗎𝗌𝗏𝖿 𝗀𝖻𝗆𝗍𝖿 𝗎𝗌𝗏𝖿 = 𝗌𝖿𝗀𝗆 𝗊𝗌𝗉𝗉𝗀𝖦𝖻𝖾𝖾𝖢𝗉𝗉𝗆 𝗎𝗌𝗏𝖿 𝗀𝖻𝗆𝗍𝖿 𝗀𝖻𝗆𝗍𝖿 = 𝗌𝖿𝗀𝗆 𝗊𝗌𝗉𝗉𝗀𝖨𝖻𝖾𝖾𝖢𝗉𝗉𝗆 ∶ ∀ 𝑏 𝑐 → ⟦ 𝗂𝖻𝖾𝖾 ⟧ (𝑏 , 𝑐) ≡ 𝗂𝖻𝖾𝖾𝖳𝗊𝖿𝖽 𝑏 𝑐 𝗊𝗌𝗉𝗉𝗀𝖨𝖻𝖾𝖾𝖢𝗉𝗉𝗆 𝑏 𝑐 = 𝖽𝗉𝗈𝗁 (_,_ (𝑏 ∧ 𝑐)) (𝗒𝗉𝗌𝖥𝗋𝗏𝗃𝗐 𝑏 𝑐)

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 21

Properties of sequential circuits

▶ Defining correctness of sequential circuits is not so trivial ▶ One (very simple) example: a shift register

𝗍𝗂𝗃𝗀𝗎 ∶ ℂ 𝖢 𝖢 𝗍𝗂𝗃𝗀𝗎 = 𝖾𝖿𝗆𝖻𝗓ℂ 𝗊𝖳𝗑𝖻𝗊 Latch in

• ut

▶ Currently working in this area

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 22

Compiling to VHDL

▶ Π-Ware shall support compiling circuits into VHDL netlists

• Main goal: generate synthesizable (IEEE 1076.3)
• Secondary: hierarchical descriptions (components)

▶ Work in progress

• More critical problems to be solved first

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 23

Compiling to VHDL

Requirements for VHDL generation:

▶ The DSL must be deep-embedded ▶ “Fundamental” gates need to have a structural definition

• Extra field of 𝖧𝖻𝗎𝖿𝗍
• Mapping each gate to a piece of VHDL abstract syntax.

▶ To support hierarchical modeling:

• Some form of “component” declaration in the circuit types
• Investigate approaches for naming
• Reflection could help

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 24

Section 3 Current / next steps

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 25

Current work

▶ Proof properties of sequential circuits

• Using bisimilarity
• For example, for the shift register we have seen:

𝗍𝗂𝗃𝗀𝗎 ∶ ℂ 𝖢 𝖢 𝗍𝗂𝗃𝗀𝗎 = 𝖾𝖿𝗆𝖻𝗓ℂ 𝗊𝖳𝗑𝖻𝗊 𝗊𝗌𝗉𝗉𝗀𝖳𝗂𝗃𝗀𝗎𝖴𝖻𝗃𝗆 ∶ ∀ {𝑗𝑜𝑡} → 𝗎𝖻𝗃𝗆 (⟦ 𝗍𝗂𝗃𝗀𝗎 ⟧∗ 𝑗𝑜𝑡) ≈ 𝑗𝑜𝑡 𝗊𝗌𝗉𝗉𝗀𝖳𝗂𝗃𝗀𝗎𝖴𝖻𝗃𝗆 = 𝗏𝗈𝖾𝖿𝗀𝗃𝗈𝖿𝖾

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 26

Current work

▶ Proof combinators

_⟫ ≡′ _ ∶ {𝑗 𝑛 𝑝 ∶ ℕ} {𝑔1 ∶ 𝖷 𝑗 → 𝖷 𝑛} {𝑔2 ∶ 𝖷 𝑛 → 𝖷 𝑝}

{𝑑1 ∶ ℂ′ 𝑗 𝑛} {𝑑2 ∶ ℂ′ 𝑛 𝑝} {𝑞1 ∶ 𝖽𝗉𝗇𝖼′ 𝑑1} {𝑞2 ∶ 𝖽𝗉𝗇𝖼′ 𝑑2} → (∀ 𝑤1 → ⟦_⟧′ {𝑗} {𝑛} 𝑑1 {𝑞1} 𝑤1 ≡ 𝑔1 𝑤1) → (∀ 𝑤2 → ⟦_⟧′ {𝑛} {𝑝} 𝑑2 {𝑞2} 𝑤2 ≡ 𝑔2 𝑤2) → (∀ 𝑤 → ⟦_⟧′ {𝑗} {𝑝} (𝑑1 ⟫′ 𝑑2) {𝑞1 𝖽𝗉𝗇𝖼⟫′ 𝑞2} 𝑤 ≡ (𝑔2 ∘ 𝑔1) 𝑤)

_⟫ ≡′ _ {𝗀𝟤 = 𝑔1} 𝑞𝑑1 𝑞𝑑2 𝑤 𝗌𝖿𝗑𝗌𝗃𝗎𝖿 𝗍𝗓𝗇 (𝑞𝑑2 (𝑔1 𝑤)) | 𝗍𝗓𝗇 (𝑞𝑑1 𝑤) = 𝗌𝖿𝗀𝗆

.

. .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. .

Intro

Quick intro Context Inspired by

Dive into Π-Ware

Circuit syntax Two levels of abstraction Semantics / Reasoning Netlists

Current / next steps

Current work Next steps 27

Next steps

▶ VHDL generation ▶ Proof automation

• Case analysis, boring proofs – reflection
• Better instance search
• Auto (Kokke, Swierstra)

.

Thank you! Questions?

. . .... .. .. ... . .... .... .... ... . .... .... .... ... . .... .... .... ... . .. .. .. . . .. .. .... .. .