Lecture 7: Sequential Networks CSE 140: Components and Design - - PowerPoint PPT Presentation

Lecture 7: Sequential Networks

CSE 140: Components and Design Techniques for Digital Systems Spring 2014

CK Cheng, Diba Mirza

• Dept. of Computer Science and Engineering

University of California, San Diego

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Sequential Networks

• Memory Components

– Hierarchy of Memory – Basic Mechanism of Memory – Types of Flip-Flops

• Implementation

– Finite State Machine

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Part II. Sequential Networks (Ch. 3)

Memory / Time steps Clock

Memory: Flip flops Specification: Finite State Machines Implementation: Excitation Tables xi yi si yi=fi(St,X) si

t+1=gi(St,X)

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What is a sequential circuit?

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“A circuit whose output depends on current inputs and past outputs” “A circuit with memory”

Why do we need circuits with ‘memory’?

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• A. Complex systems often consist of circuits that

perform a sequence of tasks

• B. Circuits with memory can be used to store data
• C. Both A and B

The connection between sequences and memory

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• What differentiates a musical piece from a cacophony?
• What is the role of memory in playing a musical piece

(essentially a sequence of notes)?

Sequential Network vs. Combinational Logic:

Q: Which of the following is FALSE?

• A. Combinational logic can replace any sequential

network to realize the same function.

• B. Sequential networks use the same set of logic

gates as combinational logic.

• C. Sequential networks can implement a CPU.
• D. Sequential networks require a precise clock for

timing.

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Hierarchy of Memory Devices

• Memory Bank (Farms of memory cells)
• Register (Vector of memory cells)
• Flip-Flop (Single memory cell)

– SR, D, T, JK flip-flops (Different types of memory cells) – State Tables (Truth table of sequential machine) – Characteristic Expressions (Switching algebraic expression of sequential machine)

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Fundamental Memory Mechanism

Q Q Q Q I1 I2 I2 I1

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Memory Mechanism: Capacitive Load

• Fundamental building block of sequential circuits
• Two outputs: Q, Q
• There is a feedback loop!
• In a typical combinational logic, there is no

feedback loop.

• No inputs

Q Q Q Q I1 I2 I2 I1

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Capacitive Loads

Q Q I1 I2 1 1

• Consider the two possible cases:

– Q = 0: then Q’ = 1 and Q = 0 (consistent) – Q = 1: then Q’ = 0 and Q = 1 (consistent) – Bistable circuit stores 1 bit of state in the state variable, Q (or Q’ )

• But there are no inputs to control the state

Q Q I1 I2 1 1

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iClicker

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• Q. Given a memory component made out of a loop
• f inverters, the number of inverters has to be
• A. Even
• B. Odd

SR (Set/Reset) Latch

R S Q Q N1 N2

• SR Latch
• Consider the four possible cases:

– S = 1, R = 0 – S = 0, R = 1 – S = 0, R = 0 – S = 1, R = 1

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SR Latch Analysis

– S = 1, R = 0: – S = 0, R = 1:

R S Q Q N1 N2 1

R S Q Q N1 N2 1

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SR Latch Analysis

– S = 1, R = 0: then Q = 1 and Q = 0 – S = 0, R = 1: then Q = 0 and Q = 1

R S Q Q N1 N2 1

R S Q Q N1 N2 1

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SR Latch Analysis

– S = 1, R = 1:

R S Q Q N1 N2 1 1

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SR Latch Analysis

– S = 0, R = 0:

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R S Q Q N1 N2

SR Latch Analysis

– S = 0, R = 0: then Q = Qprev – S = 1, R = 1: then Q = 0 and Q = 0

R S Q Q N1 N2 1 1

R S Q Q N1 N2 R S Q Q N1 N2 Qprev = 0 Qprev = 1

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S R y Q Q = (R+y)’ y = (S+Q)’

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Flip-flop Components

S R

SR F-F (Set-Reset)

Inputs: S, R State: (Q, y) y Q

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Id Q(t) y(t) S R Q(t1) y(t1) Q(t2)y(t2) Q(t3) y(t3) 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 0 1 0 1 2 0 0 1 0 1 0 1 0 1 0 3 0 0 1 1 0 0 0 0 0 0 4 0 1 0 0 0 1 0 1 0 1 5 0 1 0 1 0 1 0 1 0 1 6 0 1 1 0 0 0 1 0 1 0 7 0 1 1 1 0 0 0 0 0 0 8 1 0 0 0 1 0 1 0 1 0 9 1 0 0 1 0 0 0 1 0 1 10 1 0 1 0 1 0 1 0 1 0 11 1 0 1 1 0 0 0 0 0 0 12 1 1 0 0 0 0 1 1 0 0 13 1 1 0 1 0 0 0 1 0 1 14 1 1 1 0 0 0 1 0 1 0 15 1 1 1 1 0 0 0 0 0 0

Q y State Transition SR

10

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00 11

00 10 SR 11 10 01 11 01 11 01 10 00 10 00 01 00 11

State Diagram

01

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CASES: SR=01, (Q,y) = (0,1) SR=10, (Q,y) = (1,0) SR=11, (Q,y) = (0,0) SR = 00 => if (Q,y) = (0,0) or (1,1), the output keeps changing

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• Q. To avoid the SR latch output from toggling
• r behaving in an undefined way which input

combinations should be avoided:

• A. (S, R) = (0, 0)
• B. (S, R) = (1, 1)

SR Latch Analysis

– S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!) – S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q)

R S Q Q N1 N2 1 1

R S Q Q N1 N2 1 1 R S Q Q N1 N2 1 1 Qprev = 0 Qprev = 1

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CASES: SR=01, (Q,y) = (0,1) SR=10, (Q,y) = (1,0) SR=11, (Q,y) = (0,0) SR = 00 => if (Q,y) = (0,0) or (1,1), the output keeps changing Solutions: 1) SR = (0,0), or 2) SR = (1,1). 0 0 0 1 - 1 1 0 1 -

PS

inputs

00 01 10 11 State table Q(t+1)

SR Characteristic Expression Q(t+1) = S(t)+R’(t)Q(t)

NS (next state) Q(t)

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SR Latch Symbol

• SR stands for Set/Reset Latch

– Stores one bit of state (Q)

• Control what value is being stored with S, R inputs

– Set: Make the output 1 (S = 1, R = 0, Q = 1) – Reset: Make the output 0 (S = 0, R = 1, Q = 0)

• Must do something to avoid

invalid state (when S = R = 1)

S R Q Q SR Latch Symbol

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D Latch

D Latch Symbol CLK D Q Q

• Two inputs: CLK, D

– CLK: controls when the output changes – D (the data input): controls what the

• utput changes to
• Function

– When CLK = 1, D passes through to Q (the latch is transparent) – When CLK = 0, Q holds its previous value (the latch is opaque)

• Avoids invalid case when Q ≠ NOT Q

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D Latch Internal Circuit

CLK D Q Q

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S R Q Q SR Latch Symbol

D Latch Internal Circuit

S R Q Q Q Q D CLK

D R S

CLK D Q Q

S R Q Q CLK D X 1 1 1 D

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D Latch Internal Circuit

S R Q Q Q Q D CLK

D R S

CLK D Q Q

S R Q Qprev 1 1 1 Q 1 CLK D X 1 1 1 D X 1 Qprev

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D Flip-Flop

• Two inputs: CLK, D
• Function

– The flip-flop “samples” D on the rising edge of CLK

• When CLK rises from 0 to 1, D

passes through to Q

• Otherwise, Q holds its previous value

– Q changes only on the rising edge of CLK

• A flip-flop is called an edge-triggered device

because it is activated on the clock edge

D Flip-Flop Symbols D Q Q

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D Flip-Flop Internal Circuit

CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

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D Flip-Flop Internal Circuit

CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

• Two back-to-back latches (L1 and L2)

controlled by complementary clocks

• When CLK = 0

– L1 is transparent, L2 is opaque – D passes through to N1

• When CLK = 1

– L2 is transparent, L1 is opaque – N1 passes through to Q

• Thus, on the edge of the clock (when CLK

rises from 0 1)

– D passes through to Q

CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

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D Flip-Flop vs. D Latch

CLK D Q Q

D Q Q

CLK D Q (latch) Q (flop) 33

D Flip-Flop vs. D Latch

CLK D Q Q

D Q Q

CLK D Q (latch) Q (flop) 34

Latch and Flip-flop (two latches)

A latch can be considered as a door CLK = 0, door is shut CLK = 1, door is unlocked A flip-flop is a two door entrance CLK = 1 CLK = 0 CLK = 1

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D Flip-Flop (Delay)

D CLK Q Q’

Id D Q(t) Q(t+1) 0 0 0 0 1 0 1 0 2 1 0 1 3 1 1 1

Characteristic Expression: Q(t+1) = D(t) 0 0 1 1 0 1 PS D 0 1 State table NS= Q(t+1)

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CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

iClicker

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Can D flip-flip serve as a memory component?

• A. Yes
• B. No

JK F-F

J CLK Q Q’ 0 0 0 1 ? 1 1 0 1 ?

PS

JK 00 01 10 11

State table Q(t+1) K

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JK F-F

J CLK Q Q’

Characteristic Expression Q(t+1) = Q(t)K’(t)+Q’(t)J(t)

0 0 0 1 1 1 1 0 1 0

PS

JK 00 01 10 11

State table Q(t+1) K

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T CLK Q Q’

Characteristic Expression Q(t+1) = Q’(t)T(t) + Q(t)T’(t)

0 0 1 1 1 0 PS T 0 1 State table Q(t+1)

T Flip-Flop (Toggle)

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Using a JK F-F to implement a D and T F-F

J K Q Q’ x CLK

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iClicker What is the function of the above circuit?

• A. D F-F
• B. T F-F
• C. None of the above

Using a JK F-F to implement a D and T F-F

J K Q Q’ T CLK T flip flop

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Reading

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[Harris] Chapter 3: 3.3, 3.4.1, 3.4.2