Delta-Sigma Time to Digital Converter Using Charge Pump and SAR ADC - - PowerPoint PPT Presentation

Delta-Sigma Time to Digital Converter Using Charge Pump and SAR ADC

IEICE General Conference 2015 Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology

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Outline

• Background
• Basic concept
• Circuit design
• Simulation results
• Conclusion

4/2/2015 Anugerah Firdauzi - Tokyo Tech

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Background

• TDC Application

– 3D camera – Laser range finder – Time-of-flight (TOF) particle detector – On chip jitter measurement – PLL and frequency synthesizer

• Contradictory requirements

– High resolution (~1ps) – Wide input range (several ns)

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L L Emitter Sensor

𝑴 = 𝒅. 𝒖/𝟑 Distance measurement

TDC Digital Filter Counter Fref Fv DCO

ADPLL

Anugerah Firdauzi - Tokyo Tech

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Previous Work

• Charge pump and SAR ADC
• Time-to-charge conversion with SAR ADC 

high resolution

• SAR-ADC: compact, sufficient range, and

moderate speed

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PFD UP DN CK1 CK2 …. C V SAR-ADC Dout

𝑢𝑠𝑓𝑡 = 𝐷. 𝑊

𝑀𝑇𝐶/𝐽

• Challenge: high order SAR

ADC is required

– High design complexity – Limited speed – Large area

[Z.Xu, CICC ‘13] Anugerah Firdauzi - Tokyo Tech

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Proposal: ΔΣ TDC

• Σ is realized by charging capacitor C and never reset it
• Δ is realized by discharging/charging C through array of current

source DAC at constant time for positive/negative output

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Tin

• E

Dout z-1 z-1

Σ Δ

Anugerah Firdauzi - Tokyo Tech PFD UP DN CK1 CK2 Dout ... Logic Current source DAC

Δ

ICP ICP

Σ

C

Q t + V

• I

Q I t Δ=0.5Q I t

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Timing Diagram

• 𝜠𝑾𝒏𝒃𝒚 = ∆𝑾𝑱𝑶,𝒏𝒃𝒚 + ∆𝑾𝑬𝑩𝑫,𝒏𝒃𝒚
• 𝟐

𝟑 𝑾𝒔𝒇𝒈𝒒 − 𝑾𝒔𝒇𝒈𝒐 = 𝑱𝑫𝑸 . 𝑼𝑱𝑶,𝒏𝒃𝒚 𝑫𝑬𝑩𝑫

+

𝚻𝑱𝑬𝑩𝑫 . 𝑼𝑬𝑩𝑫 𝑫𝑬𝑩𝑫

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ΔΣ thumb rule: ∆𝑾𝑱𝑶,𝒏𝒃𝒚 = ∆𝑾𝑬𝑩𝑫,𝒏𝒃𝒚

For VOP: Charging input HIGH output  discharge LOW output  charge 1 2 3

3 UP DN VOP VON Out (delay) 1 2 1 CK1 CK2 TIN TDAC ΔVIN

• ΔVDAC

Vrefp Vrefn SAR conversion

Anugerah Firdauzi - Tokyo Tech

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Multibit Quantizer Effect

• For 𝑴𝒖𝒊 order ΔΣ ADC with 𝑶 bit quantizer:
• 𝑻𝑶𝑺𝒆𝑪 = 𝟐𝟏 log

𝟒𝝆 𝟑

𝟑𝑶 − 𝟐

𝟑 𝟑𝑴 + 𝟐 𝑷𝑻𝑺 𝝆 𝟑𝑴+𝟐

• 𝑭𝑶𝑷𝑪 = (𝑻𝑶𝑺𝒆𝑪 − 𝟐. 𝟖𝟕)/𝟕. 𝟏𝟑
• Increasing quantizer size by one can improve ENOB 1-1.5 bit

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• Target:

– 1st order ΔΣ TDC – Quantizer 4 bit – OSR = 100 – ENOB = 13 bit

5 10 15 20 25 30 1 10 100 1000 ENOB OSR [L,N] [5,4] [4,4] [3,4] [2,4] [1,7] ↓ [1,1] Target

Anugerah Firdauzi - Tokyo Tech

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• Ideal model using MATLAB
• 4 bit quantizer
• Input = ±1ns at 52kHz
• BW

= 1MHz

• OSR = 100
• Result:
• ENOB > 11bit
• Effective resolution < 0.9ps

Simulation Result

4/2/2015 Anugerah Firdauzi - Tokyo Tech

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4

10

5

10

6

10

7

10

8

• 160
• 140
• 120
• 100
• 80
• 60
• 40
• 20

Frequency [Hz] PSD [dB]

SNDR = 72.42 dB ENOB = 11.74 bit SNDR = 73.63 dB ENOB = 11.94 bit

1ps noise ideal 20dB/dec 1ns input BW

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Conclusion

• A new approach for TDC by using ΔΣ

architecture is proposed.

• ΔΣ TDC implemented by using CP SAR

ADC, and current source DAC gives first

• rder noise shaping and high resolution

for moderate bandwidth while keeping the input range large and power consumption low

4/2/2015 Anugerah Firdauzi - Tokyo Tech