[PDF] - Deep Underground Neutrino Experiment (DUNE) 1 Technical Proposal 2 PDF Document

SLIDE 1

Deep Underground Neutrino Experiment (DUNE)

1

Technical Proposal

2

23 Feb 2018: First draft of the TP volumes due

3

Volume 2: The Single-Phase Far Detector

4

February 26, 2018

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SLIDE 2

1

SLIDE 3

List of Figures

1

1.1 Connections between the signal flange and APA at ProtoDUNE-SP. The interface be-

2

tween the electronics chain, the APAs, and the cryostat will be very similar at the DUNE

3

far detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4

1.2 APA wire bias schematic diagram, including the CR board. . . . . . . . . . . . . . . . . 8

5

1.3 The CE architecture. The basic unit is the 128-channel FEMB. . . . . . . . . . . . . . 9

6

1.4 The complete FEMB assembly as used in the ProtoDUNE-SP detector. The cable shown

7

is the high-speed data, clock, and control cable. . . . . . . . . . . . . . . . . . . . . . 10

8

1.5 Measured pulse response with details on gain, peaking time and baseline adjustments. . 11

9

1.6 Baseline cold ADC ASIC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 12

10

1.7 Block diagram of COLDATA ASIC design. . . . . . . . . . . . . . . . . . . . . . . . . 14

11

1.8 Prototype CE Box used in ProtoDUNE-SP. . . . . . . . . . . . . . . . . . . . . . . . . 15

12

1.9 Overall architecture of the CRYO ASIC. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

13

1.10 Depiction of the substrate isolation technique that allows combining analog and digital

14

circuitry on the same CRYO ASIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15

1.11 Block diagram of the DRE architecture for the ATLAS ADC ASIC. . . . . . . . . . . . 18

16

1.12 Block diagram depicting the two-stage SAR design of the ATLAS ADC ASIC. . . . . . . 18

17

1.13 TPC CE feedthrough. The WIBs are seen edge-on in the left panel,and in an oblique

18

side-view in the right panel, which also shows the warm crate for a DUNE module in a

19

cutaway view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

20

1.14 Exploded view of the signal flange for ProtoDUNE-SP. . . . . . . . . . . . . . . . . . . 21

21

1.15 Power and Timing Card (PTC) and timing distribution to the WIB and FEMBs. . . . . 22

22

1.16 LV power distribution to the WIB and FEMBs. 250W is for a fully-loaded crate with the

23

majority of the power dissipated by the 20 cold FEMBs in the LAr. . . . . . . . . . . . 22

24

1.17 Warm Interface Board (WIB). Note that front panel inputs include a LEMO connector

25

and alternate inputs for LV power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

26

1.18 FCi micro TCA power connector at the PTC end of the cable. . . . . . . . . . . . . . . 24

27

1.19 ENC (in electrons) and temperature (in degrees Kelvin) as a function of cold cycle time

28

in GN2 for ProtoDUNE-SP APA2. At the lowest temperature of 160K, the wrapped

29

wires measured 480e− noise and the straight wires 400e−. . . . . . . . . . . . . . . . . 30

30

1.20 Picture of the shielded room at Fermilab. . . . . . . . . . . . . . . . . . . . . . . . . . 32

31

1.21 Left: one side of the 40% APA with 4 FEMBs. Right: the full CE feedthrough and flange. 32

32 33

iii

SLIDE 6

List of Tables

1

1.1 TPC electronics components and quantities for the DUNE single-phase far detector. . . 3

2

1.2 Baseline cold ADC ASIC configurability. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3

1.3 Performance requirements for the ATLAS-style ADC ASIC. . . . . . . . . . . . . . . . . 17

4 5

iv

SLIDE 7

Todo list

1

There are some placeholders for citations here; need to revisit how to cite e.g. interface

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documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

3

This section will be written for the second draft of the technical proposal. . . . . . . . . 33

4

This section will be written for the second draft of the technical proposal. . . . . . . . . 35

5

Please note that these dates may need to be revisited and that there may be more

6

time available prior to the beginning of construction. . . . . . . . . . . . . . . . . . 36

7

This section will be written for the second draft of the technical proposal. . . . . . . . . 37

8

This section will be written for the second draft of the technical proposal. . . . . . . . . 37

9

v

SLIDE 8

Chapter 1: TPC Electronics 1–1

Chapter 1

1

TPC Electronics

2

ch:fdsp-tpc-elec

1.1 System Overview

3

sec:fdsp-tpc-elec-ov

1.1.1 Introduction

4

sec:fdsp-tpc-elec-ov-intro

The DUNE single-phase TPC readout electronics are often referred to as the “Cold Electronics”

5

(CE) given that they reside in the liquid argon, mounted directly on the APA. The charge carrier

6

mobility in silicon is higher and thermal fluctuations are lower at liquid argon temperature than at

7

room temperature. For CMOS electronics, this results in substantially higher gain and lower noise

8

at liquid argon temperature than at room temperature

LArCMOS

[54]. Mounting the front-end electronics

9

n the APA frames also minimizes the input capacitance. Furthermore, placing the digitizing and

10

multiplexing (MUX) electronics inside of the cryostat allows for a reduction in the total number

11

f penetrations into the cryostat and minimizes the number of cables coming out of the cryostat,

12

reducing the expense and complexity of the experiment. As the full TPC electronics chain for

13

the single-phase detector includes many components on the warm side of the cryostat as well, the

14

DUNE consortium designated to organize CE development is referred to as the DUNE “Single-

15

Phase TPC Electronics” consortium.

16

The lower noise levels (by about a factor of two) enabled by having the front-end electronics in the

17

cold greatly extends the reach of the DUNE physics program

LArCMOS

[54]. The CP violation and neutrino

18

mass ordering measurements depend on a precise characterization of the reconstructed neutrino

19

energy spectrum; improving the charge resolution as much as possible (by lowering noise levels in

20

the wire readout) allows for one to better resolve features in reconstructed neutrino energy spectrum

21

that are relevant for these physics measurements. Decreasing the noise level also allows for smaller

22

charge deposits to be measurable, which acts as a source of risk mitigation in the case that the

23

electron lifetime in the detector is lower than desired (due to the prevelance of electronegative

24

impurities in the detector), and also increases the reach of low-energy physics measurements such

25

as those associated with stellar core-collapse supernova burst neutrinos. Finally, the low noise

26

levels allows the experiment to utilize low-energy 39Ar beta decays for the purpose of precision

27

calibration in the DUNE far detector.

28

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SLIDE 9

Chapter 1: TPC Electronics 1–2

An extensive discussion of the TPC electronics system design is given in Section

sec:fdsp-tpc-elec-design

1.2. What

1

immediately follows is a brief overview of the major design considerations for the cold electronics

2

to be used in the DUNE single-phase far detector.

3

1.1.2 Design Considerations

4

sec:fdsp-tpc-elec-ov-consid

The CE signal processing is implemented in application-specific integrated circuit (ASIC) chips

5

using CMOS technology, which has been demonstrated to perform well at cryogenic temperatures,

6

and includes amplification, shaping, digitization, buffering, and multiplexing (MUX) of the signals.

7

The CE is continuously read out, resulting in a digitized ADC sample from each APA channel (wire)

8

up to every 500 ns (2 MHz sampling rate).

9

Each individual APA has 2,560 channels that are read out by 20 Front-End Motherboards (FEMBs),

10

with each FEMB providing digitized wire readout from 128 channels. One cable bundle connects

11

each FEMB to the outside of the cryostat via a feedthrough (a CE feedthrough) in the signal

12

cable flange at the top of the cryostat, where a single flange services each APA, as shown in Fig-

13

ure

fig:connections

1.1. Each cable bundle contains wires for low-voltage (LV) power, high-speed data readout, and

14

clock/digital-control signal distribution. Eight separate cables carry the TPC wire-bias voltages

15

from the signal flange to the APA wire-bias boards.

16

Figure 1.1: Connections between the signal flange and APA at ProtoDUNE-SP. The interface between the electronics chain, the APAs, and the cryostat will be very similar at the DUNE far detector.

fig:connections

The components of the CE system are the following:

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SLIDE 10

Chapter 1: TPC Electronics 1–3

front-end mother boards, which house the cold ASICs and are installed on the APAs;

1

cables for the data, clock/control signals, LV power, and wire-bias voltages between the APA

2

and the signal flanges (cold cables);

3

signal flanges with a CE feedthrough to pass the data, clock/control signals, LV power, and

4

APA wire-bias voltages between the inside and outside of the cryostat;

5

warm interface electronics crates (WIECs) that are mounted on the signal flanges and contain

6

the warm interface boards (WIBs) and power and timing cards (PTCs) for further processing

7

and distribution of the signals entering/exiting the cryostat;

8

fiber cables for transmitting data and clock/control signals between the WIECs and the data

9

acquisition (DAQ) and slow control systems;

10

cables for LV power and wire-bias voltages between the signal flange and external power

11

supplies (warm cables); and

12

LV power supplies for the CE and bias-voltage power supplies for the APAs.

13

The electrical cables for each APA enter the cryostat through a single signal flange, creating an

14

integrated unit that provides local diagnostics for noise and validation testing, and follows the

15

grounding guidelines in Section

sec:fdsp-tpc-elec-design-ground

1.2.1. The components, the quantity of each required for the

16

DUNE far detector, and the number of channels that each component has, are listed in Table

tab:elecNums

1.1.

17

Table 1.1: TPC electronics components and quantities for the DUNE single-phase far detector. Element Quantity Channels per element APA 150 2,560 Front-end mother board (FEMB) 20 per APA 128 FE ASIC chip 8 per FEMB 16 ADC ASIC chip 8 per FEMB 16 COLDATA ASIC chip 2 per FEMB 64 Cold cable bundle 1 per FEMB 128 Signal flange 1 per APA 2,560 CE feedthrough 1 per APA 2,560 Warm interface board (WIB) 5 per APA 512 Warm interface electronics crate (WIEC) 1 per APA 2,560 Power and timing card (PTC) 1 per APA 2,560 Passive Backplane (PTB) 1 per APA 2,560

tab:elecNums

The baseline design for the DUNE far detector single-phase TPC electronics calls for three types

18

f ASICs to be located inside of the liquid argon:

19

a 16-channel front-end (FE) ASIC including amplification and pulse shaping;

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SLIDE 11

Chapter 1: TPC Electronics 1–4

a 16-channel 12-bit ADC ASIC operating at 2 MHz; and

1

a 64-channel control and communications ASIC.

2

The front-end ASIC has been prototyped and is close to meeting requirements (discussed in Sec-

3

tion

sec:fdsp-tpc-elec-ov-req

1.1.3). Key portions of the control and communications ASIC (also referred to as the COL-

4

DATA ASIC) have been prototyped and meet requirements. However, it has been determined that

5

the ADC ASIC now being used in ProtoDUNE-SP does not meet requirements, and accordingly,

6

its development has been terminated. A new cold ADC ASIC is being developed by an LBL-

7

FNAL-BNL collaboration and first prototypes are expected by the end of summer 2018. The first

8

full prototype of the controls and communication ASIC is also expected to be available for testing

9

by the end of the summer 2018. In order to maximize the probability of developing a complete

10

design for cold TPC front-end electronics in a timely fashion, an alternative solution is also being

11

investigated, a single 64-channel ASIC that will include all three functions described above. This

12

design is being done at SLAC and first prototypes are expected late in spring or early summer

13

2018.

14

A series of tests are planned to demonstrate that at least one of these designs will meet DUNE

15

requirements. These include two system tests: one using the ProtoDUNE “cold box” at CERN,

16

and one using a new small liquid argon TPC at Fermilab. The latter will also accommodate one

17

half-length DUNE photodetector, and will provide a low noise environment that will allow one to

18

make detailed comparisons of the performance of the new ASICs. It will also enable the study

19

f interactions between the TPC readout and other systems, including the photodetector readout

20

and the HV distribution. These test facilities are discussed in more detail in Section

sec:fdsp-tpc-elec-qa-facilities

1.5.2.

21

1.1.3 System Requirements

22

sec:fdsp-tpc-elec-ov-req

The core components of the TPC electronics subsystem are the FEMB ASICs that perform shaping,

23

digitization, and multiplexing of channel data in the cold. Two basic requirements for the ASIC

24

designs are:

25

negligible risk of failure due to the hot carrier effect (less than 0.7% channel failure per APA

26

plane in 30 years of operation); and

27

a total power consumption of less than 50 mW/channel.

28

If multiple ASIC designs meet these two requirements, the down-select decision will be based

29

n performance, power consumption, estimated reliability, and estimated cost. Of these factors,

30

performance will be given the largest weight.

31

For the FE ASICs, more specific requirements include:

32

less than 1000e− equivalent noise charge (ENC) in LAr for the induction channels;

33

baseline recovery for large pulses;

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SLIDE 12

Chapter 1: TPC Electronics 1–5

crosstalk between neighboring channels below the 2% level;

1

crosstalk between non-neighboring channels well below the 1% level;

2

a nonlinearity below the 0.5% level or precisely characterized; and

3

channel-to-channel gain uniformity that is either negligible or precisely characterized.

4

A secondary performance measurement is dynamic range. If noise or linearity depends on the gain

5

setting, then most weight (90%) will be given to the setting with best performance for which an

6

impulse of 85 fC at the input does not saturate the output.

7

Additional ADC ASIC requirements are:

8

an associated noise level that is less than 0.5 least significant bits (LSB);

9

a usable dynamic range of at least 3000:1;

10

differential nolinearity (DNL) that is less than 1 LSB; and

11

integrated nonlinearity (INL) that is either less than 1 LSB or consistent from channel-to-

12

channel and chip-to-chip.

13

Finally, specific requirements of the COLDATA ASIC design include:

14

fully functional at both room temperature and liquid argon temperature; and

15

both control and data links must operate with negligible error rate over cables up to 21 m

16

in length.

17

In addition to these requirements on the ASICs, the TPC electronics subsystem must also:

18

provide the means to read out the TPC wires and transmit their data in a useful format to

19

the DAQ;

20

operate for the life of the facility without significant loss of function;

21

record the channel waveforms continuously without dead time;

22

be constructed only from materials that are compatible with high-purity LAr;

23

provide sufficient precision and range in the digitization to discriminate electrons from pho-

24

ton conversions, optimize the reconstruction of high-energy and low-energy tracks from

25

accelerator-neutrino interactions, distinguish a minimum-ionizing particle (MIP) from noise

26

with a signal-to-noise ratio of 9:1 or greater, and measure ionization up to 15 times that of

27

a MIP so that stopping kaons from proton decay can be identified;

28

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SLIDE 13

Chapter 1: TPC Electronics 1–6

ensure that all poewr supplies have local monitoring and control, remote monitoring and

1

control through the DAQ, and over-current and over-voltage protection circuits; and

2

ensure that the CE feedthroughs are able to withstand twice their nominal operating voltages

3

with a maximum specified leakage current in 1-atm argon gas.

4

The quality assurance (QA) process, described in Section

sec:fdsp-tpc-elec-qa

1.5, will make use of both initial valida-

5

tion procedures using electronics test stands as well as integrated test facilities in order to ensure

6

that final component designs satisfy the above requirements. Once component designs have been

7

decided upon, the quality control (QC) process will employ similar requirements to make sure that

8

every component to be installed in the DUNE single-phase far detector is up to standard. This is

9

described in more detail in Section

sec:fdsp-tpc-elec-qc

1.6.

10

1.2 System Design

11

sec:fdsp-tpc-elec-design

1.2.1 Grounding and Shielding

12

sec:fdsp-tpc-elec-design-ground

The goal of the cold electronics system design is to minimize inherent system noise at the input of

13

the FE pre-amplifier while providing sufficient precision and dynamic range to achieve the DUNE

14

physics goals, as detailed in Section

sec:fdsp-tpc-elec-ov-consid

1.1.2. To accomplish this, the electrical cables for each APA

15

enter the cryostat through a single signal flange, creating an integrated unit that provides local

16

diagnostics for noise and validation testing.

17

To avoid structural ground loops, the APA frames described in Section APAFRAME are insulated

18

from each other. Each frame is electrically connected to the cryostat at a single point on the CE

19

feedthrough board in the signal flange where the cables exit the cryostat. Mechanical suspension

20

f the APAs is accomplished using insulated supports.

21

The analog portion of the FEMB contains eight front-end ASICs configured as 16-channel digitizing

22

charge amplifiers. Input amplifiers on the ASICs have their ground terminals connected to the

23

APA frame. All power-return leads and cable shields are connected to both the ground plane of

24

the FEMB and to the signal flange.

25

Filtering circuits for the APA wire-bias voltages are locally referenced to the ground plane of the

26

FEMBs through low-impedance electrical connections. This approach ensures a ground-return

27

path in close proximity to the bias-voltage and signal paths. The close proximity of the current

28

paths minimizes the size of potential loops to further suppress noise pickup.

29

Photon detector signals, described Section PD, are carried directly on shielded, twisted-pair cables

30

to the signal flange. The cable shields are connected to the cryostat at a second feedthrough, the

31

PDS feedthrough, and to the PCB shield layer on the photon detectors. There is no electrical

32

connection between the cable shields and the APA frame except at the signal flange.

33

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SLIDE 14

Chapter 1: TPC Electronics 1–7

The frequency domain of the TPC wire and photon detector signals are separate. The wire readout

1

digitizes at 2 MHz with < 500 kHz bandwidth at 1 µsec peaking time, while the photon readout

2

perates at 150 MHz with > 10 MHz bandwidth. They are separated from the clock frequency

3

(50 MHz) and common noise frequencies through the FE ASIC and cabling designs. All clock

4

signals are transmitted differentially with individual shield to avoid the interference to power

5

lines.

6

1.2.2 Distribution of Wire-Bias Voltages

7

sec:fdsp-tpc-elec-design-bias

Each side of an APA includes four wire layers as described in Section APADESIGN. The innermost

8

X-plane layer of wires is nominally biased at +820 Volts, with each wire AC coupled to one of

9

the 128 charge amplifier circuits on the FEMB. The V-plane wire layer is effectively biased at

10

zero volts, with each wire directly connected to one of the charge amplifier circuits. The U-plane

11

wire layer is nominally biased at −370 Volts with each wire AC-coupled to one of the 128 charge

12

amplifier circuits. The outermost G-plane wire layer, which has no connection to the charge

13

amplifier circuits, is biased at −665 Volts.

14

Electrons passing through the wire grid must drift unimpeded until they reach the X-plane col-

15

lection layer. The nominal bias voltages are predicted to result in this electrically transparent

16

configuration.

17

As described in Section APAWIRE the filtering of wire-bias voltages and AC coupling of wire

18

signals passing onto the charge amplifier circuits is done on capacitance-resistance (CR) boards

19

that plug in between the APA wire-board stacks and FEMBs. Each CR board includes single

20

R-C filters for the X- and U-plane wire-bias voltages. In addition, each board has 48 pairs of bias

21

resistors and AC coupling capacitors for X-plane wires, and 40 pairs for the U-plane wires. The

22

coupling capacitors block DC while passing AC signals to the CE motherboards. A schematic

23

diagram of the APA wire bias subsystem is illustrated in Figure

fig:CR-board

1.2.

24

Separate CR boards include a single R-C filter for the G-plane wires and 12 pairs of bias resistors

25

and coupling capacitors. Groups of four wires are tied together to share single bias resistors and

26

filter capacitors. These CR boards do not connect to the charge amplifier circuits on the FEMB.

27

Clamping diodes limit the input voltage received at the amplifier circuits to between 1.8V ± U_D,

28

where U_D is the breakdown voltage of the diode ∼0.7V. The amplifier circuit has a 22-nF coupling

29

capacitor at input to avoid leakage current from the protection clamping diodes.

30

Coupling capacitors for the X-plane and U-plane wires are required to block DC bias voltages.

31

However they also impact the efficiency of the detector circuits. The sense wires are expected

32

to have ∼ 200 pF of capacitance to the APA frame. Induced or collected charges are effectively

33

divided between the wire capacitance and the coupling capacitor. To achieve a charge-calibration

34

accuracy of 0.5 percent or better, the coupling capacitors must be 4.7 nF at ten percent tolerance,

35

r 2.2 nF at five percent tolerance.

Voltage ratings should be at least 1.5 times the expected

36

perating voltages.

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23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 15

Chapter 1: TPC Electronics 1–8

Figure 1.2: APA wire bias schematic diagram, including the CR board.

fig:CR-board

Bias resistance values should be at least 20 MΩ to maintain negligible noise contributions. A

1

target value of 50 MΩ is desired. The higher value helps to achieve a longer time constant for the

2

high-pass coupling networks. Time constants should be at least 25 times the electron drift time so

3

that the undershoot in the digitized waveform is small and easily correctable. However, leakage

4

currents can develop on PC boards that are exposed to high voltages over extended periods. If the

5

bias resistors are much greater than 50 MΩ, leakage currents may affect the bias voltages applied

6

to the wires.

7

The bias-voltage filters are R-C low-pass networks. Resistance values should be much smaller than

8

the bias resistances to control crosstalk between wires and limit the voltage drop if any of the wires

9

becomes shorted to the APA frame. A value around 2.2 MΩ is desired. Smaller values may be

10

considered although a larger filter capacitor would be required to maintain a given level of noise

11

reduction. A target value of 47 nF has been established for the filter capacitors.

12

For the grid-plane bias filters, component values are less critical. If possible they will be identical

13

to those used for the bias resistors and coupling capacitors (50 MΩ and 2.2 to 4.7 nF).

14

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SLIDE 16

Chapter 1: TPC Electronics 1–9

1.2.3 Front-End Mother Board (FEMB)

1

sec:fdsp-tpc-elec-design-femb

The main component of the CE architecture, illustrated in Figure

fig:ce-scheme

1.3, is the 128-channel FEMB,

2

which itself consists of an analog motherboard and an attached COLDATA mezzanine card for

3

processing the digital outputs. Each APA is instrumented with 20 FEMBs, for a total of 2,560

4

channels per APA. The FEMBs plug directly into the APA CR boards, making the connections

5

from the U- and V-plane induction wires and X-plane collection wires to the charge amplifier

6

circuits as short as possible.

7 COLDATA COLDATA

Figure 1.3: The CE architecture. The basic unit is the 128-channel FEMB.

fig:ce-scheme

1.2.3.1 Overview

8

sec:fdsp-tpc-elec-design-femb-ov

The analog mother board is instrumented with eight 16-channel FE ASICs, eight 16-channel ADC

9

ASICs, LV power regulators, and input-signal protection circuits. The 16-channel FE ASIC pro-

10

vides amplification and pulse shaping. The 16-channel ADC ASIC comprises 12-bit digitizers

11

performaning at speeds up to 2 MS/s, local buffering, and an 8:1 MUX stage with two pairs of

12

serial readout lines in parallel. The 2017 ProtoDUNE Single Phase (ProtoDUNE-SP) version of

13

the FEMB is shown in Figure

fig:femb

1.4.

14

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SLIDE 17

Chapter 1: TPC Electronics 1–10

Figure 1.4: The complete FEMB assembly as used in the ProtoDUNE-SP detector. The cable shown is the high-speed data, clock, and control cable.

fig:femb

1.2.3.2 Front-End ASIC

1

sec:fdsp-tpc-elec-design-femb-fe

Each FE ASIC channel has a charge amplifier circuit with a programmable gain selectable from

2

ne of 4.7, 7.8, 14 and 25 mV/fC (full scale charge of 55, 100, 180 and 300 fC), a high-order anti-

3

aliasing filter with programmable time constant (peaking time 0.5, 1, 2, and 3 µs), an option to

4

enable AC coupling, and a baseline adjustment for operation with either the collecting (200 mV)

5

r the non-collecting (900 mV) wires. Shared among the 16 channels in the FE ASIC are the bias

6

circuits, programming registers, a temperature monitor, an analog buffer for signal monitoring,

7

and the digital interface. The estimated power dissipation of FE ASIC is about 6 mW per channel

8

at 1.8 V supply.

9

The ASIC was implemented using the commercial CMOS process (0.18 µm and 1.8 V), which is

10

expected to be available for at least another 10 years. The charge amplifier input MOSFET is a

11

p-channel biased at 2 mA with a L/W (channel length/width) ratio of 0.27 µm / 10 µm, followed

12

by dual cascade stages.

13

Each channel also implements a high-performance output driver, which can be used to drive a

14

long cable, but is disabled when interfaced to an ADC ASIC to reduce the power consumption.

15

The ASIC integrates a band-gap reference (BGR) to generate all the internal bias voltages and

16

currents. This guarantees a high stability of the operating point over a wide range of temperatures,

17

including cryogenic. The ASIC is packaged in a commercial, fully encapsulated plastic QFP 80

18

package.

19

Each FE ASIC channel is equipped with an injection capacitor which can be used for test and

20

calibration and can be enabled or disabled through a dedicated register. The injection capaci-

21

tance has been measured using a calibrated external capacitor. The measurements show that the

22

calibration capacitance is extremely stable, changing from 184 fF at RT to 183 fF at 77 K. This

23

result and the measured stability of the peaking time demonstrate the high stability of the passive

24

components as a function of temperature. Channel-to-channel and chip-to-chip variation in the

25

calibration capacitor are typically less than 1%.

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Chapter 1: TPC Electronics 1–11

4
2

2 4 6 8 0.0 0.2 0.4 0.6 0.8 Amplitude [V] Time [µs] T=300K T=77K Gain 25 mV/fC Peaking time 1µs Pole-zero cancellation at 77K to be addressed in next revision

⎩ ⎨ ⎧ ° ° ≈ K 77 at V 164 . 1 K 300 at V 185 . 1 VBGR

Bandgap Reference

10 20 30 40 50 Amplitude [a.u.] Time [µs] Peak time [µs] 0.5 1.0 2.0 3.0 collecting mode non-collecting mode gain [mV/fC] 25 14 7.8 4.7

Adjustable gain , peaking time and baseline

maximum charge 55, 100, 180, 300fC

variation = 1.8 % ⎩ ⎨ ⎧ ° ° ≈ K 77 at V m 3 . 259 K 300 at mV . 867 VTMP

Temperature Sensor ~ 2.86 mV / K

Figure 1.5: Measured pulse response with details on gain, peaking time and baseline adjustments.

fig:fe-output

Prototype ASICs have been evaluated and characterized at RT (300 K) and LN2 (77 K) temper-

1

ature. During testing the circuits have been cycled multiple times between the two temperatures

2

and operated without any change in performance. Figure

fig:fe-output

1.5 shows the measured pulse response,

3

both as a function of temperature and the programmable settings of the chip. These results are

4

in close agreement with simulations and indicate that both the analog and the digital circuits and

5

interface operate as expected in a cryogenic environment.

6

1.2.3.3 ADC ASIC

7

sec:fdsp-tpc-elec-design-femb-adc

The baseline option for the DUNE Cold ADC is a 16-channel low-noise ADC ASIC intended to read

8

ut the LARASIC preamps in the DUNE cold electronics. The resolution of the ADC is 12 bits

9

and it digitizes at a rate of 2 MS/s/channel. The ADC accepts single-ended or differential inputs,

10

and outputs a serial data stream to COLDATA, the DUNE digital serializer chip. The ADC ASIC

11

is implemented using 65 nm CMOS technology. The ASIC uses a conservative, industry standard

12

design along with digital calibration. A block diagram of the ADC ASIC is shown in Figure

fig:adc-blockdiagram

1.6.

13

Each Cold ADC receives 16 single-ended voltage outputs from a single LARASIC chip. The voltage

14

is buffered and then sampled at a rate of 2 MS/s. The analog samples are multiplexed by 8 and

15

digitized by calibrated 12-bit pipelined ADCs operating at 16 MS/s. The ADC uses the well-known

16

Pipelined architecture with redundancy to reduce the impact of component non-idealities on the

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Chapter 1: TPC Electronics 1–12

S/H Correction Logic Data Formatter IN0 IN7 I2C DIG_OUTA(P/N) DIG_OUTB(P/N) I2C_(SCL,SDA, SDO) CLK_64MHZ(P/N) S/H 12-bit 16 MS/s Pipelined ADC DIG_FRAME(P/N) DIG_CLKOUT(P/N) Ref Generation and Buffers

Cold ADC

8-1 MUX DIG_OUTC(P/N) DIG_OUTD(P/N) LVDS I/O BUFFER BUFFER S/H Correction Logic IN8 IN15 S/H 12-bit 16 MS/s Pipelined ADC 8-1 MUX BUFFER BUFFER UART MISO/MOSI Configuration and Debug Interface Async FIFO Async FIFO IMONITOR VMONITOR DIG_OUTE(P/N) DIG_OUTF(P/N) DIG_OUTG(P/N) DIG_OUTH(P/N) CLK_16MHZ(P/N) CLK_2MHZ(P/N) I2C_ADD SSO_(FRAME, DATA[1:0], CLK) VREF(P,N,CMI,CMO), BGR VDD/VSS domains LVDS_REF Calibration Engine Calibration Engine 30 30 16 30 16 16

Figure 1.6: Baseline cold ADC ASIC block diagram.

fig:adc-blockdiagram

linearity of the ADC

121557

[50]. The linearity of the raw output samples from the ADCs is improved

1

using an on-chip calibration. The corrected ADC output is then multiplexed onto eight LVDS

2

channels and sent to COLDATA for further aggregation and transmission via a copper link to the

3

warm electronics sitting outside the cryostat.

4

The ADC ASIC is designed for low-noise operation. The noise specification is 175 ÂţV-rms. This

5

noise specification was chosen to ensure that LARASIC will dominate the overall noise performance

6

f the channel.

7

The ADC is digitally calibrated using the proven Soenen-Karanicolas algorithm

280084,372864

[51, 52]. The

8

algorithm exploits the observation that in a pipelined ADC with redundancy, the ADC nonlinearity

9

is caused almost entirely by errors in the closed-loop interstage gain

121557

[50]. Traditionally, the ADC

10

utput bits are assumed to be in radix 2 and are simply combined to generate the ADC output.

11

However, due to unavoidable non-idealities such as finite op-amp gain and capacitor mismatch,

12

the true radix of each stage is slightly different from two. The extent to which the true radix

13

is different from two leads to DNL and INL in the ADC transfer characteristic. The Soenen-

14

Karanicolas algorithm provides a way to measure the radix of a given stage by forcing events

15

at the decision boundaries and using the following stages of the ADC to record the stageâĂŹs

16

response. The radix is then decomposed into a set of weights and during normal operation the

17

ADC output is converted from the true radix to radix 2 using pipelined digital adders. This

18

way, static linearity can be greatly improved without any post-processing required. To provide

19

additional ease-of-use, all calibration hardware (including test signal generation) is included on the

20

ADC ASIC. To control power dissipation, the stages of the ADC are scaled in area in power to take

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Chapter 1: TPC Electronics 1–13

advantage of the fact that the accuracy requirements of the stages decline down the pipeline

494191

[53].

1

To reduce the number of pads and to improve performance all required reference voltages and

2

currents are generated internally by a resistor-programmed reference generator on the ASIC.

3

The Cold ADC is highly configurable (see Table

tab:ADCconfig

1.2) and includes two redundant slow control

4

interfaces for configuration (either UART or I2C). The configurability of the chip is included

5

primarily to reduce risk by providing a high degree of flexibility and observability. First, many of

6

the components on the ASIC can be bypassed and their functions assumed at the board level if

7

desired. For example, the ADC reference voltages can be supplied externally and the input buffers

8

can be bypassed. Second, the ADC digital calibration algorithm can be implemented externally

9

with the calculated stage weights loaded back into the chip using the configuration interface. Third,

10

various internal voltages and currents can be monitored and test data can be introduced at various

11

parts of the digital processing to observe the function of the ASIC. Lastly, the bias point of the

12

analog circuits in the ASIC can be adjusted to compensate for expected component variations

13

between room temperature and liquid Argon temperature.

14

Table 1.2: Baseline cold ADC ASIC configurability. BLOCK Configurability Comment Input Buffer Single-ended/differential, bypass, bias current adjust Reduces design risk Sample-and-hold Amplifiers Multiplexer freeze, bias current adjust Simplifies evaluation of prototype ADC Bias currents, clock edge fine adjustment, sync and test modes Simplifies evluation of prototype and reduces risk References All reference voltages can be adjusted in 8 mV in- crements; all references can be powered down and external voltages used Reduces design risk Calibration Number of stages and amount of digital filtering; all calibration commands can be implemented through configuration interface for offline calibration; known data can be injected at various points for testing Simplifies evaluation of prototype and reduces risk Output Monitor Various internal bias voltages and currents can be sent off-chip for evaluation Simplifies evaluation of prototype

tab:ADCconfig

1.2.3.4 COLDATA ASIC

15

sec:fdsp-tpc-elec-design-femb-coldata

The COLDATA ASIC is responsible for all communication between the cold TPC electronics

16

n FEMBs and electronics located outside the cryostat. Each FEMB contains two COLDATA

17

ASICs. COLDATA receives command and control information. It provides clocks to the Cold

18

ADC ASICs and relays commands to the LArASIC front-end and to the Cold ADC ASICs to

19

set operating modes and initiate calibration procedures. COLDATA receives data from the ADC

20

ASICs, reformats these data, merges data streams, formats data packets, and sends these data

21

packets to the warm electronics using 1.28 Gbps links. These links are designed for use with 30

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Chapter 1: TPC Electronics 1–14

m long cables and include line drivers with pulse preemphasis. A block diagram of COLDATA is

1

shown in Figure

fig:coldata

1.7.

2

Figure 1.7: Block diagram of COLDATA ASIC design.

fig:coldata

COLDATA is designed in 65 nm CMOS using “cold” transistor models based on data collected by

3

members of the FNAL, BNL, and SMU ASIC groups. A special library of standard cells, based

4

n these models and using a minimum channel length of 90 nm, was developed by members of the

5

U. Pennsylvania and FNAL groups. This library was designed to eliminate the risk posed by the

6

hot carrier effect. The digital sections of COLDATA use these standard cells and were synthesized

7

from RTL using automatic place and route tools. Key circuit elements of COLDATA, including

8

the control interface and the PLL and serializer, were prototyped successfully in 2017. Submission

9

f a full chip is expected in June 2018.

10

1.2.3.5 Cold Electronics Box

11

sec:fdsp-tpc-elec-design-femb-box

Each FEMB is enclosed in a mechanical “Cold Electronics Box” to provide support, cable strain

12

relief, and control of gas Argon bubbles in the LAr from the FEMB attached to the lower APA. As

13

shown in Figure

fig:ce-box

1.8, the CE Box is designed to make the electrical connection between the FEMB

14

and the APA frame, as defined in Section

sec:fdsp-tpc-elec-design-ground

1.2.1. Mounting hardware inside the CE Box connects

15

the ground plane of the FEMB to the box casing. The box casing is electrically connected to the

16

APA frame via twisted conducting wire (not shown in Figure

fig:ce-box

1.8). This is the only point of contact

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Chapter 1: TPC Electronics 1–15

between the FEMB and APA, except for the input amplifier circuits connected to the CR board,

1

which also terminate to ground at the APA frame, as shown in Figure

fig:CR-board

1.2.

2

Figure 1.8: Prototype CE Box used in ProtoDUNE-SP.

fig:ce-box

1.2.4 Additional FEMB/ASIC Designs

3

sec:fdsp-tpc-elec-design-alt

In addition to the baseline FEMB and ASIC designs discussed in Section

sec:fdsp-tpc-elec-design-femb

1.2.3, there are other

4

FEMB and ASIC options currently being considered as well. This allows for risk mitigation in the

5

case that the baseline ADC ASIC design does not pass the requirements laid out in Section

sec:fdsp-tpc-elec-ov-scope

??.

6

There is one official alternative design, the SLAC-designed nEXO three-chip “CRYO” ASIC, and

7

ne fallback option for the ADC ASIC, the Columbia-led ATLAS-style ADC ASIC. These options

8

are described in Section

sec:fdsp-tpc-elec-design-alt-cryo

1.2.4.1 and Section

sec:fdsp-tpc-elec-design-alt-atlas

1.2.4.2, respectively.

9

1.2.4.1 nEXO CRYO ASIC

10

sec:fdsp-tpc-elec-design-alt-cryo

The SLAC CRYO ASIC differs from the "baseline" three-chip design in that it combines the

11

functions of an analog pre-amp, ADC and data serialization/transmission, for 64 wire channels,

12

into a single chip. It is based on a design developed for the nEXO experiment and differs from it

13

nly in the design of the preamplifier, which is modified to account for the higher capacitance of

14

the DUNE wires compared to the small pads of nEXO. FEMBs constructed using this chip would

15

use only 2 ASICs compared to the 18 (8 FE, 8 ADC and 2 COLDDATA) neeeded in the baseline

16

design. This drastic reduction in part-count may significantly improve FEMB reliablity. reduce

17

power, and reduce costs related to production and testing.

18

Figure

fig:cryo-architecture

1.9 shows the overall architecture of the CRYO ASIC, which will be implemented in 130

19

nm CMOS. It comprises two identical, 32-channel blocks. The current signal from each wire is

20

amplified using a pre-amp with pole zero cancellation and an anti-alias fifth-order Bessel filter

21

applied. Provisions is also made for injection of test pulses. Gain and peaking time are adjustable

22

to values similar to those of the baseline design.

23

The ADC is 8 MSPS Successive Approximation Registration (SAR), so that four input channels are

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Chapter 1: TPC Electronics 1–16

Figure 1.9: Overall architecture of the CRYO ASIC.

fig:cryo-architecture

multiplexed onto a single ADC. The data serialization and transmission block employs a custom

1

12b/14b encoder, so that 32 channels of 12 bit, 2 MSPS data can be transmitted with a digital

2

bandwidth of only 896 Mb/s, which is significantly less than the required bandwidth of the baseline,

3

which is 1.27 Gb/s.

4

One key concern with "mixed signal" ASICs is the possibility of interference from the digital side

5

causing noise on the very sensitive pre-amp. Fortunately, there are well established techniques

6

for "substrate isolation" described in the literature

yeh

[49], which have been successfully employed

7

in previous ASICs produced by the SLAC group. Figure

fig:cryo-substrate

1.10 shows how substrate isolation is

8

achieved.

9

The infrastructure requirements for a CYRO ASIC-based system are similar to those of the baseline

10

ption. However, in most cases, somewhat fewer resources are needed:

11

A single voltage is needed for the power supply. This is used to generate two supply voltages

12

using internal voltage regulators.

13

The output digital bandwidth on each of the four lines in an FEMB is 896 Mb/s. This is

14

lower than the baseline option due to the custom 12b/14b encoder of the CRYO chip.

15

The warm interface is different. Only a single clock is needed (56 MHz) and the configuration

16

protocol is SACI rather than I2C.

17

The first prototype of the CRYO ASIC is in the final design and simulation stages. Simulation-

18

based studies have already been performed; at 0.8 µS peaking time, the ENC is approximately

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Chapter 1: TPC Electronics 1–17

Figure 1.10: Depiction of the substrate isolation technique that allows combining analog and digital circuitry on the same CRYO ASIC.

fig:cryo-substrate

500e−. Submission to the ASIC foundry is imminent and the first protypes should be received in

1

April. They will first be tested in an existing test stand at SLAC. Subsequent tests are planned

2

for a small test TPC at FNAL and on an APA in the ProtoDUNE-SP cold box; these test facilities

3

are described in Section

sec:fdsp-tpc-elec-qa-facilities

1.5.2.

4

1.2.4.2 ATLAS ADC ASIC

5

sec:fdsp-tpc-elec-design-alt-atlas

An alternative ADC solution is to adapt the ADC chip under development for the ATLAS liquid

6

argon calorimeter readout upgrade for the HL-LHC. The main ATLAS requirements are given

7

in Table

tab:ATLAS-ADC-reqs

1.3. Adapting the chip to DUNE needs would require doubling the number of channels

8

per chip as well as adapting the output architecture. These are both relatively simple changes

9

compared to the overall complexity of the chip.

10

Table 1.3: Performance requirements for the ATLAS-style ADC ASIC. Parameter Specification Channels/chip 8 preferred, 4 minimum Sampling Frequency 40 MHz Dynamic Range 14 bits Precision 11 ENOB Power < 100 mW/channel at 40 MHz Input 2 V differential Output E-link interface operating at 640 Mbps

tab:ATLAS-ADC-reqs

To achieve a 14-bit dynamic range, each analog channel is comprised of two main sections: a

11

Dynamic Range Enhancement (DRE) block that determines the most significant two bits of the

12

14-bit digital code, followed by a 12-bit SAR block.

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Chapter 1: TPC Electronics 1–18

The design of the DRE is shown schematically in Figure

fig:65nmADCarchitecture_dre

1.11. The input signal is sampled on two

1

paths, one with unity gain and the other of gain four. A comparator determines which gain to

2

use. The signal from the selected DRE gain is presented at the DRE output, which is connected

3

to the input of the 12-bit SAR ADC block. The DRE design has been carefully optimized so that

4

its output preserves the required 12-bit performance.

5

Figure 1.11: Block diagram of the DRE architecture for the ATLAS ADC ASIC.

fig:65nmADCarchitecture_dre

Figure 1.12: Block diagram depicting the two-stage SAR design of the ATLAS ADC ASIC.

fig:65nmADCarchitecture_sar

More details of the SAR design are shown in Figure

fig:65nmADCarchitecture_sar

1.12. Following current state-of-the-art

6

ADC development techniques, a two-stage SAR architecture is used, exploiting the high speed

7

f the technology while maintaining the SAR input capacitance at a reasonable value.

Since

8

capacitor matching in this technology might not meet the precision required, the ADC will use bit

9

redundancy, i.e. determine more bits than its actual output, and the redundant bits will be used

10

to both calibrate the ADC and produce correct output codes. Such procedures are well understood

11

and applied to both pipeline

Kuppambatti:2013nfa

[47] and SAR

5999734

[48] ADCs using foreground or background calibration

12

techniques.

13

An ADC testchip, dubbed COLUTA65V1, was designed and submitted for fabrication in May

14

2017 and received in September of 2017. The DRE and SAR blocks of the COLUTA65V1 were

15

first tested independently. Measurements were made of the SAR precision using the sine-wave

16

Fast Fourier Transform method. An effective number of bits (ENOB) of 11.6 bits at 20 MHz

17

(after calibration) was obtained. Similar measurements at 40 MHz do not match the expected

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SLIDE 26

Chapter 1: TPC Electronics 1–19

performance and additional testing and simulation indicates that the layout of the connection

1

between the first SAR stage and the amplifier is not optimal. Similar results were observed with

2

the DRE performance and again simulation indications improvements are possible in the layout.

3

The next submission of the chip, planned for spring 2018, will incorporate this work in the iteration

4

f the design. Both DRE and SAR were successfully integrated with negligible degradation in

5

performance. The COLUTA65V1 chip was also tested at 2 MHz and shown to work as designed.

6

Tests in liquid nitrogen are planned for spring 2018.

7

1.2.5 Cold Electronics Feedthroughs and Cold Cables

8

sec:fdsp-tpc-elec-design-ft

All cold cables originating from inside the cryostat connect to the outside warm electronics through

9

PCB board feedthroughs installed in the signal flanges that are distributed along the cryostat roof.

10

The TPC data rate per APA, with an overall 32:1 MUX and 80 ∼1 Gbps data channels per APA,

11

is sufficiently low that the LVDS signals can be driven over copper twin-axial transmission lines.

12

Additional transmission lines are available for the distribution of LVDS clock signals and I2C

13

control information, which are transmitted at a lower bit rate. Optical fiber is employed externally

14

from the WIBs on the signal flange to the DAQ and slow control systems.

15

Figure 1.13: TPC CE feedthrough. The WIBs are seen edge-on in the left panel,and in an oblique side-view in the right panel, which also shows the warm crate for a DUNE module in a cutaway view.

fig:tpcelec-signal_FT

The design of the signal flange includes a T-shaped pipe, separate PCB feedthroughs for the CE

16

and PDS cables, and an attached crate for the TPC warm electronics, as shown in Figure

fig:tpcelec-signal_FT

1.13. The

17

wire-bias voltage cables connect to standard SHV (safe high voltage) connectors machined directly

18

into the CE feedthrough, ensuring no electrical connection between the wire-bias voltages and other

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SLIDE 27

Chapter 1: TPC Electronics 1–20

signals passing through the signal flange. Each CE feedthrough serves the bias/power/digital IO

1

needs of one APA.

2

Data/control cable bundles are used to send system clock and control signals from the signal flange

3

to the FEMB, stream the ∼1 Gbps high-speed data from the FEMB to the signal flange. Each

4

FEMB connects to a signal flange via one data cable bundle, leading to 20 bundles between one

5

APA and one flange. Each data bundle contains 8 low-skew copper twin-axial cables with a drain

6

wire, to transmit the following differential signals:

7

4×1.2 Gbps high-speed data

8

One 100 MHz clock

9

One 2 MHz CONVERT clock

10

2 I2C control and configure

11

The selected cables are Samtec 26 AWG twin-axial bundles with connectors to both the FEMB

12

mezzanine board and the signal flange. Each twin-axial pair is separately shielded. The Samtec

13

26 AWG cable has been tested and demonstrated to have low enough dispersion such that both

14

the LVDS 50 MHz system clock and ∼1 Gbps high-speed data can be recovered over 30 meters of

15

RT cable.

16

LV power is passed from the signal flange to the FEMB by bundles of 20 AWG twisted-pair wires.

17

Half of the wires are power feeds; the other wires are attached to the grounds of the input amplifier

18

circuits, as described in Section

sec:fdsp-tpc-elec-design-bias

1.2.2. For a single FEMB, the resistance is measured to be < 30 mΩ

19

at RT or < 10 mΩ at LAr temperature. Each APA has a copper cross-section of approximately

20

80 mm2, with a resistance < 1.5 mΩ at RT or < 0.5 mΩ at LAr temperature.

21

The wire-bias voltage cables are required to deliver voltages up to a few thousand Volts and

22

currents up to a few milliAmps.

23

The bias voltages are applied to the X-, U-, and G-plane wire layers, three field cage terminations,

24

and an electron diverter, as shown in Figure

fig:CR-board

1.2. The voltages are supplied through eight SHV

25

connectors mounted on the signal flange. RG-316 coaxial cables carry the voltages from the signal

26

flange to a patch panel PCB which includes noise filtering mounted on the top end of the APA.

27

From there, wire-bias voltages are carried by single wires to various points on the APA frame,

28

including the CR boards, a small PCB mounted on or near the patch panel that houses a noise

29

filter and termination circuits for the field cage voltages, and a small mounted board near the

30

electron diverter that also houses wire-bias voltage filters.

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Chapter 1: TPC Electronics 1–21

1.2.6 Warm Interface Electronics

1

sec:fdsp-tpc-elec-design-warm

The warm interface electronics are housed in warm interface electronics crates (WIECs) attached

2

directly to the signal flange. The WIEC shown in Figure

fig:tpcelec-flange

1.14 contains one Power and Timing

3

Card (PTC), up to five Warm Interface Boards (WIBs) and a passive Power and Timing Backplane

4

(PTB), which fans out signals and LV power from the PTC to the WIBs.

5

Figure 1.14: Exploded view of the signal flange for ProtoDUNE-SP.

fig:tpcelec-flange

The WIB is the interface between the DAQ system and up to four FEMBs. It receives the system

6

clock and control signals from the timing system and provides for processing and fan-out of those

7

signals to the four FEMBs. The WIB also receives the high-speed data signals from the four

8

FEMBs and transmits them to the DAQ system over optical fibers. The data signals are recovered

9

nboard the WIB with commercial equalizers. The WIBs are attached directly to the TPC CE

10

feedthrough on the signal flange. The feedthrough board is a PCB with connectors to the cold

11

signal and LV power cables fitted between the compression plate on the cold side, and sockets for

12

the WIB on the warm side. Cable strain relief for the cold cables is supported from the back end

13

f the feedthrough.

14

The PTC provides a bidirectional fiber interface to the timing system. The clock and data streams

15

are separately fanned-out to the five WIBs as shown in Figure

fig:tpcelec-wib_timing

1.15. The PTC fans the clocks out

16

to the WIB over the PTB, which is a passive backplane attached directly to the PTC and WIBs.

17

The received clock on the WIB is separated into clock and data using a clock/data separator.

18

The PTC also receives LV power for all cold electronics connected through the signal flange,

19

approximately 250W at 48V for a fully-loaded flange (one PTC, five WIB, and 20 FEMB). The

20

LV power is then stepped down to 12V via a DC/DC converter onboard the PTC. The output of

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23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 29

Chapter 1: TPC Electronics 1–22

SFP Rx SFP Tx

Fanout 1:6 MUX 6:1 Prio. Enc.

SFP Rx

ADN2814

Clock/Data Recovery Arria V FPGA

Fanout 1:4 Fanout 1:4

PLL

MUX MUX

SFP Tx

Clock to FEMBs

Clock to MBs Encoded Control to MBs

Reply Data Reply enable Control to FEMBs

Power/Timing Backplane

Primary Clock/Control Path through PTC Alternative Clock/Control Path through WIB front panel Laser Enable Reply Data

WIB PTC

Encoded Clock+ Control MUX Encoded clock/control

Figure 1.15: Power and Timing Card (PTC) and timing distribution to the WIB and FEMBs.

fig:tpcelec-wib_timing

Arria 5 GX/T WIB

DC-DC Front Panel FEMB 0 FEMB 1 FEMB 2 FEMB 3 1.5V 2.5V 2.8V 3.6V Enable

Power in 48V (~250W)

DC-DC DC-DC Bias 0-3 linear

To FEMBs

Sense fuse

PTC 5

Fanout 1:5

12V 12V

PTB

48V/12V DC-DC

Figure 1.16: LV power distribution to the WIB and FEMBs. 250W is for a fully-loaded crate with the majority of the power dissipated by the 20 cold FEMBs in the LAr.

fig:tpcelec-wib_power

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 30

Chapter 1: TPC Electronics 1–23

the PTC converters is filtered with a common-mode choke and fanned out on the PTB to each

1

WIB, which provides the necessary 12V DC/DC conversions and fans the LV power out to each of

2

the cold FEMBs supplied by that WIB, as shown in Figure

fig:tpcelec-wib_power

1.16. The output of the WIB converters

3

are further filtered by a common-mode choke. The majority of the 250W drawn by a full flange is

4

dissipated in the LAr by the cold FEMB.

5

Each WIB contains a unique IP address for its UDP slow control interface. The IP address for the

6

WIB is derived from a crate and slot address: the crate address is generated on the PTC board via

7

dipswitches and the slot address is generated by the PTB slot, numbered from one to five. Note

8

that the WIBs also have front-panel connectors for receiving LV power; these can be used in place

9

f the LV power inputs on the PTB generated by the PTC.

10

The WIB is also capable of receiving the encoded system timing signals over bi-directional optical

11

fibers on the front panel, and processing these using either the on-board FPGA or clock synthesizer

12

chip to provide the 50 MHz clock required by the cold electronics.

13

Figure 1.17: Warm Interface Board (WIB). Note that front panel inputs include a LEMO connector and alternate inputs for LV power.

fig:tpcelec-dune_wib

The FPGA on the WIB is an Altera Arria V GT variant, which has transceivers that can drive

14

the high-speed data to the DAQ system up to 10.3125 Gbps per link, implying that all data from

15

two FEMB (2×5 Gbps) could be transmitted on a single link. The FPGA has an additional

16

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Chapter 1: TPC Electronics 1–24

Gbps Ethernet transceiver I/O based on the 125 MHz clock, which provides real-time digital data

1

readout to the slow control system.

2

1.2.7 External Power and Supplies

3

sec:fdsp-tpc-elec-design-external

Including power for the WIB, a fully loaded WIB (one WIB plus four FEMBs) requires 12V and

4

draws up to approximately 4 Amps. Therefore, the full electronics for one APA (one PTC, five

5

WIBs, and 20 FEMBs) requires 12V and draws approximately 20A, for a total power of almost

6

250W, as described in Section

sec:fdsp-tpc-elec-design-warm

1.2.6.

7

As the LV power is delivered at 48V to the PTC, each LV power mainframe should operate at

8

roughly 30-60V/13.5A/650W maximum capacity. Using 10 AWG cable, an 0.8V drop is expected

9

along the cable with a required power of 306.12W out of 650W available.

10

Four wires will be used for each module, two 10 AWG, shielded, twisted pair for the power and

11

return, two 20 AWG, shielded, twisted pair for the sense. Sense line fusing will be provided on

12

the PTC card. This fusing would serve as a final protection. The primary protection would come

13

from the Over Current protection on the LV supply modules, which is set above the ∼20 Amps.

14

The LV power cable uses FCi micro TCA connectors, shown in Figure

fig:tpcelec-power_conn

1.18.

15

Figure 1.18: FCi micro TCA power connector at the PTC end of the cable.

fig:tpcelec-power_conn

Each APA requires three wire-bias voltage connections at +820V, −370V, and −665V, as described

16

in Section

sec:fdsp-tpc-elec-design-bias

1.2.2. The remaining five wire-bias voltage lines supply between 1 and 1.5 kV to the field

17

cage terminations (3) and electron diverters (2). The current on each of these supplies is expected

18

to be zero at normal operation. However the ripple voltage on the supply must be carefully

19

controlled to avoid noise injection into the front-end electronics. Each HV module supplies all the

20

wire-bias power to one APA via 8 SHV connector feedthroughs at the CE flange.

21

RG-58 coaxial cables connect the wire bias voltages from the mini-crate to the standard SHV

22

connectors machined directly into the CE feedthrough, so there is no electrical connection between

23

the LV power and data connectors and wire-bias voltages. The length of the cables from the

24

Weiner mainframe to the signal flanges is estimated to be 18 meters.

25

Optical fibers provide the connections between the WIECs, which act as Faraday-shielded boxes,

26

to the DAQ and slow control systems.

27

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Chapter 1: TPC Electronics 1–25

Duplex LC optical fiber transmits the one GIG-E connection from each WIB to the slow control

1

system. The WIB reports its onboard temperature and the current draw from each FEMB to the

2

slow control system, while the current draw for each APA is monitored at the mainframe itself.

3

1.3 Production and Assembly

4

sec:fdsp-tpc-elec-prod

A single 10 kt DUNE single phase detector requires 3000 FEMBs, 750 WIBs, and 50 PTCs. A

5

total of 3300 FEMBs, 900 WIBs, and 60 PTCs will be built.

6

If the three-ASIC FEMB solution is chosen, then two ASIC production contracts will be required,

7

ne for LArASIC (180 nm CMOS) and one for the cold ADC and COLDATA (65 nm CMOS). If

8

the one-ASIC FEMB solution is chosen, only one ASIC production contract will be required.

9

In either case, all ASICs will be packaged in Plastic Quad Flat-Pack (PQFP) or Thin Quad

10

Flat-Pack (TQFP) surface mount packages. No wafer probing will be done before the chips are

11

packaged. Rather, the wafers will be diced and all chips located more than

10 mm from the

12

utside of the wafer will be selected for packaging. The packaged parts will be tested by DUNE

13

collaborators (see Section

sec:fdsp-tpc-elec-qc

1.6) before being assembled onto printed circuit boards.

14

All printed circuit boards will be fabricated and tested by qualified vendors. Circuit boards will

15

also be assembled by qualified vendors. The completed boards will be acceptance tested by DUNE

16

collaborators promptly after assembly.

17

All cable assemblies (including terminations) will be fabricated and tested by qualified vendors.

18

At least a fraction of the cable assemblies will be retested by DUNE collaborators promptly after

19

purchase.

20

1.4 Interfaces

21

sec:fdsp-tpc-elec-intfc

1.4.1 Overview

22

sec:fdsp-tpc-elec-intfc-ov

There are some placeholders for citations here; need to revisit how to cite e.g. interface documents.

23

Some of the components designed and built by the CE consortium are mounted or need to work

24

together with detector components provided by other DUNE consortia. Interface documents have

25

been developed to ensure that the boundaries between systems are fully understood and that no

26

detector components is missed or not properly defined when organizing the detector construction

27

project into consortia. These interface documents are a work in progress. With time they will

28

evolve into a very detailed definition of mechanical and electrical interfaces, including in some

29

cases the description of data transmission protocols. These interface documents include a list

30

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Chapter 1: TPC Electronics 1–26

f the responsibilities of each consortium during the R&D, design, and prototyping phase, and

1

discuss also all the procedures to be followed during the integration of detector components and

2

the following testing and commissioning process. In some cases multiple consortia (APA, PDS,

3

HV, CISC, and DAQ) can be involved, depending on the complexity and maturity of the test

4

setup.

5

The most important interfaces for the CE consortium are with the APA (cite: interface : didceapa)

6

and DAQ (cite: interface : didcedaq) consortia, followed by those with the PDS (cite: interface :

7

didpdsce), HV (cite: interface : didhvce), and CISC (cite: interface : didciscce) consortia. One

8

f the most important aspects of all these interfaces is the enforcement of appropriate grounding

9

rules and of the separation between electrical circuits to minimize the noise and cross-talk between

10

different detector components. Different APAs should be electrically insulated, and the same

11

should apply for the photon detection system and the CE readout of the anode planes. The

12

flanges on the chimneys are used to provide, separately for the two APAs and for the photon

13

detector system, the reference voltage for all the detector elements. The flanges are electrically

14

connected to the cryostat structure that acts as the detector ground. The same approach has to

15

be implemented also for the CISC instrumentation in the LAr.

16

1.4.2 APAs

17

sec:fdsp-tpc-elec-intfc-apa

The CE consortium provides all the electronics used for reading out the charge deposited on the

18

APA wires by particles that ionize the LAr. The APA consortium is responsible for all the printed

19

circuit boards mounted on the APA frame holding the anode wires. These boards provide filtering

20

f the wire-bias voltages, connection of the bias voltages to the wires and AC or direct coupling

21

f the wire signals to the Front-End Motherboards (FEMBs) built by the CE consortium. The

22

FEMBs are also mounted on the APAs and are connected electrically to the CR boards. The CE

23

consortium is responsible for providing the bias voltage to the APAs, and also the bias voltage for

24

the electron diverters and the field cage termination electrodes (these last two items are part of

25

the interface with the HV consortium). The bias voltages are generated in power supplies housed

26

in crates on top of the cryostat, that are brought into the LAr using connectors on the flange

27

mounted on the CE chimneys, and then via cables to the SHV boards mounted on the APA frame

28

from where they are distributed to the various detector components.

29

A crucial aspect of the interface between the CE and APA consortia is the choice of routing for

30

the cables that provide power, control, and read-out for the bottom APA. Studies are ongoing to

31

understand whether it is feasible to route these cables inside the APA frames of the two stacked

32

APAs, and whether it is necessary to modify the size of the APA frame in order to achieve this

33

goal. Mockups of the APA frames will be used for routing tests together with protoDUNE cables,

34

under the assumption that there will be minimal changes in the cross section of cables between

35

protoDUNE and DUNE (we expect to be able to remove one of the seven pairs of power lines used

36

in protoDUNE, when the FPGA on the FEMB is replaced by the COLDATA ASIC). Before Spring

37

2019 we expect to perform a realistic test of the cable insertion in a pair of stacked APAs using

38

mechanical prototypes (i.e. without wires) of the APA. We are also investigating the possibility

39

f routing the cables for the bottom APA outside the field cage, which increases significantly

40

the length of the cables for the central APA, and complicates the installation procedure and the

41

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Chapter 1: TPC Electronics 1–27

engineering of the support structures inside the cryostat.

1

1.4.3 DAQ

2

sec:fdsp-tpc-elec-intfc-daq

There are two components in the definition of the interface between the CE and DAQ consortia.

3

The first one is a decision on whether to implement any firmware and buffering related to the

4

trigger decision inside the WIB, or instead transmit the data as they are produced from the

5

FEMBs, possibly with some serialization taking place in the WIB. For the single phase TPC we

6

have chosen to adopt the latter option, which minimizes the requirements on the FPGA inside the

7

WIB, and also reduces the power and cooling requirements for the WIC. Based on this decision,

8

the interface between the CE and DAQ consortia is defined by the fibre plant used to transmit the

9

data from the WIBs to the DAQ components housed in the Central Utility Cavern (CUC), and

10

to broadcast the clock and controls in the opposite direction. Only optical links are used in the

11

connection with the DAQ, which guarantees that the DAQ electronics will not induce any noise

12

n the APA wires.

13

The interface is fully defined with the selection of the number and type of optical fibre links, their

14

speed, and the type of connectors. The FPGA inside the WIB can be used to reformat the data

15

with changes to the headers and trailers that include time stamps and geographical addresses of

16

the FEMBs. It can also be used to serialize the data from multiple COLDATA ASICs into a single

17

stream. In the simplest scheme each electrical link from the FEMB is routed to a single optical

18

fibre, transmitting data at 1.28 Gbit/s. Depending on the availability and cost of transmitters

19

capable of sending data at higher speeds data from multiple electrical links (4, 8 or more) could be

20

serialized onto a single link, reducing the number of fibres and connections needed. Using higher

21

transmission speeds reduces the number of links that are needed, possibly reducing the cost of

22

the DAQ part of the detector. The use of links at speeds of 5 Gbit/s or larger may also present

23

another drawback, in addition to the increases in the cost of fibres, transmitters and receivers. We

24

desire to keep the data of a single FPGA into a single set of DAQ boards, without deserializing

25

the data on the CUC side. Given the granularity of the FEMBs there may be combinations of

26

ithe number of DQ boards and the number of links being used, that cannot be operated for this

27

reason. The final choice of the number of fibres, link speed and matching between FEMBs and

28

DAQ processing units in the CUC can be delayed until the Technical Design Report.

29

Another aspect of the interface between the DAQ and the CE consortia is the transmission of

30

clock and commands. In protoDUNE there is a single fibre that carries this information to the

31

PTC card, which then re-broadcasts the information to the five WIBs, using the WIC backplane.

32

For DUNE we foresee the possibility of transmitting the information directly to each WIB. This

33

would only require the addition of a receiver on each WIB, and no changes to the FPGA firmware,

34

given that already in the protoDUNE scheme the clock and control information is already decoded

35

inside the FPGA mounted in the WIB. The final aspect of the interface between the DAQ and the

36

CE is the definition of the format of the data transmitted by the cold electronics to the DAQ. This

37

format has been defined for protoDUNE in (cite: proto : dataformat). Some changes are needed

38

for DUNE, to accommodate a larger number of APAs. More extensive changes may be needed if

39

the SLAC CRYO ASIC is selected for the detector’s construction as in that case 64b/66b encoding

40

is used intedad of 8b/10b.

41

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Chapter 1: TPC Electronics 1–28

1.5 Quality Assurance

1

sec:fdsp-tpc-elec-qa

1.5.1 Initial Design Validation

2

sec:fdsp-tpc-elec-qa-initial

The QA for the DUNE single-phase far detector electronics has been ongoing for several years. It

3

includes testing all of the cold components, cables, feedthrough and flange mechanicals, and warm

4

electronics for suitability for the SP detector requirements. The current status of the QA program

5

is the instrumenting of the ProtoDUNE-SP detector with 120 FEMB (960 of each of the current

6

FE and ADC ASIC designs) and 6 full APA readout chains as described in Section

sec:fdsp-tpc-elec-design

1.2.

7

The FE ASIC

sec:fdsp-tpc-elec-design-femb-fe

1.2.3.2 design is fairly mature, and has been tested extensively on the bench and in

8

integrated system tests. The ADC ASIC will be selected from several design options as described in

9

Section

sec:fdsp-tpc-elec-design-femb-adc

1.2.3.3 and Section

sec:fdsp-tpc-elec-design-alt

1.2.4. The ADC candidates will be tested at the institutions responsible

10

for developing the designs. The COLDATA ASIC is a new design for DUNE

sec:fdsp-tpc-elec-design-femb-coldata

1.2.3.4, and will be

11

tested individually at Fermilab both standalone and communicating to FE ASICs currently on

12

FEMB analog motherboards. All tests will be done at both room temperature and in liquid

13

nitrogen.

14

The next step will be a redesign of the FEMB to accommodate the new ADC and COLDATA.

15

The current design of the FEMB for ProtoDUNE-SP uses a 16-channel, 2 MHz ADC to digitize

16

the output of the FE ASICs. Correspondingly, the modification to the baseline ADC option (if

17

used) for DUNE will be fairly minor. Prototypes of the DUNE FEMB will be tested individually

18

at several institutions at both room temperature and in liquid nitrogen. The cold data and LV

19

cables used in ProtoDUNE-SP have been selected to be candidates for DUNE and already verified

20

to successfully transmit the high-speed data over ∼ 35 meters, the longest possible cable length in

21

the far detector.

22

The updates to the DUNE mechanical components and warm interface electronics are expected to

23

be small iterations on the already existing system for ProtoDUNE-SP. Prototypes will be ordered

24

in small batches and tested at the responsible institutions for the different components.

25

After individual testing, integrated system tests will be critical to validate that the performance

26

f the CE meets the DUNE FD requirements. Issues identified in the integrated system tests will

27

be fed back into the design of the individual components.

28

1.5.2 Integrated Test Facilities

29

sec:fdsp-tpc-elec-qa-facilities

DUNE will plan for system tests of the baseline and alternative option in both the CERN cold

30

box and a small test TPC at Fermilab. The cold box tests establish performance of the electronics

31

coupled to a full-scale APA in a correctly grounded environment, but in a gaseous environment no

32

colder than 150K, and without TPC drift. The small test TPC will provide tests in an operational

33

LArTPC but at much smaller scale, with quick turn around (2-4 weeks) for changing components

34

and refilling. The 40% APA at BNL employs liquid nitrogen instead of liquid argon, does not

35

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Chapter 1: TPC Electronics 1–29

integrate the CE with the PDS, and has no TPC drift. However, it allows for quick turn-around

1

and is located very close to where the development is happening (BNL and Fermilab), and is thus

2

invaluable for initial board and component testing.

3

Generic board and component testing often includes (a) the measurement of the baseline noise

4

level and frequency spectrum, (b) the measurement of the response to the calibration input signal

5

provided on the FEMB, and (c) the measurement of the response to cosmic rays in a TPC.

6

Measurements are often done at both room temperature and liquid nitrogen or argon temperature

7

in three configurations: nothing attached to the inputs, dummy capacitive load attached to the

8

inputs, and an APA attached to the inputs as the capacitive coupling of long wires is subtly

9

different than a dummy capacitor with the equivalent capacitance of a single wire. Measurements

10

specific to the characterization of the ADC performance, such as INL and DNL determination, are

11

done before the ADC is mounted on the FEMB.

12

1.5.2.1 ProtoDUNE-SP

13

sec:fdsp-tpc-elec-qa-facilities-pdune

ProtoDUNE-SP is intended to be a full slice of the DUNE far detector as near as possible to the

14

final DUNE Single Phase design. It will instrument 6 full-size DUNE APAs with 20 FEMB each

15

for a total readout channel count of 15,360 digitized sense wires. Critically, the CE on each APA

16

will be read out via a full CE read out system, via a CE flange and WIEC with 5 WIBs and 1

17

PTC. Each APA will also have a full Photon Detector readout system installed.

18

Once each APA has been validated in the Cold Box at CERN, it will be installed in the ProtoDUNE-

19

SP cryostat. Any issues that are discovered either during the Cold Box tests or the ProtoDUNE-SP

20

commissioning and data-taking will be incorporated into the next iteration of the system design

21

for DUNE.

22

Preliminary results from the ProtoDUNE-SP cold box indicate that the noise performance of the

23

TPC readout will satisfy the DUNE FD noise requirements of ENC < 700e− on DUNE length

24

wires. The ENC and temperature of APA2 in the Cold Box are shown in Figure

fig:cb_results

1.19.

25

Tests have also been done on the ProtoDUNE-SP APA to check for any additional noise introduced

26

n the TPC wire readout by operating the PD system or enabling the wire-bias HV system. So

27

far, no significant increase in the noise on the APA wire readout has been observed when operating

28

these other systems.

29

1.5.2.2 Small Test TPC

30

sec:fdsp-tpc-elec-qa-facilities-small

A small test TPC is essential to qualifying the different prototype ASICs, offering quick turn

31

around for changing components and refilling and a TPC drift and thus the ability to study the

32

response of the electronics to signals from cosmic ray muons. A new reduced-size APA will be

33

constructed, with as many similarities to the DUNE APAs and field cage as possible. The APA

34

will be half the width of a DUNE APA (along the beam direction) or 1.3 m, with half the number

35

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Chapter 1: TPC Electronics 1–30

Figure 1.19: ENC (in electrons) and temperature (in degrees Kelvin) as a function of cold cycle time in GN2 for ProtoDUNE-SP APA2. At the lowest temperature of 160K, the wrapped wires measured 480e− noise and the straight wires 400e−.

fig:cb_results

f readout channels.

This amounts to 10 FEMBs with a total of 1280 channels. The height

1

will be significantly reduced from the DUNE APA height of 6 m to about 1.25 m, and the wire

2

lengths will be reduced by the same factor. The ProtoDUNE wire carrier boards will be used,

3

and the APA will accommodate a single half-length photon detector. The TPC will have the

4

APA in the center and a cathode on either end, creating two drift volumes with drift distance

5

0.5 m each. The TPC will be installed in the cryostat with the wire planes parallel to the floor

6

to optimize the orientation of the cosmic ray tracks. It will be instrumented with a full readout

7

chain of ProtoDUNE electronics, specifically the cables, feedthrough flange, WIB, PTC and warm

8

interface crate. Initially, ProtoDUNE FEMBs will be used for commissioning, and later FEMBs

9

with prototype ASICs will be swapped in.

10

The TPC electronics and photodetector will be read out through a “slice” of the ProtoDUNE

11

data acquisition system. This system will provide a low noise environment that will allow one to

12

make detailed comparisons of the performance of the new ASICs. It will also enable the study

13

f interactions between the TPC readout and other systems, including the photodetector readout

14

and the HV distribution.

15

The APA will be housed in new LAr cryostat at Fermilab (in the Proton Assembly Building)

16

that complies with the DUNE grounding and shielding requirements, and connected to an existing

17

recirculation system for argon purification. The cryostat will be a vertical cylinder, inner depth

18

f 185 cm and inner diameter of 150 cm. With the cryogenic connections on the upper portion of

19

the cylinder, the flat top plate will have penetrations dedicated to readout and cryogenic instru-

20

mentation. The target date for the fabrication of new front-end motherboards is fall 2018, and

21

these will house the latest version of the FE ASIC, the first prototype of COLDATA and various

22

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 38

Chapter 1: TPC Electronics 1–31

ADC prototypes (including the SLAC CRYO ASIC). The new APA and the new cryostat will be

1

completed on the same timescale so that tests in both the ProtoDUNE cold box at CERN and the

2

test TPC at Fermilab can be completed and analyzed prior to the submission of the TDR.

3

1.5.2.3 Additional Test Facilities

4

sec:fdsp-tpc-elec-qa-facilities-other

For CE development, testing prototypes at room temperature is the first step, as many problems

5

can be identified quickly and without the expense of cryogens. A quick access test stand with

6

the FEMB connected to an APA inside a shielded environment that is in the same location as

7

the FEMB/ASIC development is invaluable for rapid progress. Two such facilities are available to

8

DUNE: the shielded room at Fermilab and the 40% APA test stand at BNL. In addition, a “cold

9

box” at CERN used in electronics tests for ProtoDUNE-SP is available for additional electronics

10

testing in cold argon gas.

11

The shielded room at Fermilab (see Figure

fig:shieldedroom

1.20) is 2.5 m tall, and 2 m on each side, with a double

12

layer of copper mesh in the walls, floor and ceiling, plus a solid metal plate in the floor all electrically

13

connected to create a faraday cage. A flexible AC distribution and isolated grounding configuration

14

ffers the ability to easily ground the shielded room and power the associated electronics from either

15

a building reference or a detector reference. In addition to evaluating different grounding schemes

16

for the APAs, capacitive coupling issues can be studied by varying the distance between the floor

17

and a copper plate positioned underneath. This room has uniquely easy access to the setup

18

through a shielded door, and a person can remain inside safely with the door closed and probe the

19

electronics directly while operating in a shielded environment. Currently mounted inside are two

20

35-ton APAs with adaptor boards to connect ProtoDUNE electronics. This installation satisfies the

21

ProtoDUNE grounding and shielding guidelines. A rough demonstration of the shielding adequacy

22

for our purposes is the measured noise level of 800 ENC for ProtoDUNE prototype FEMBs. The

23

same noise level was measured at room temperature in the 40% APA at BNL for the same FEMBs.

24

The 40% APA at BNL is a 2.8 m × 1.0 m three-plane APA with two layers of 576 wrapped

25

(U/V) wires and one layer of 448 straight (X) wires. It is read out by 8 ProtoDUNE-SP FEMBs

26

with the full 7 m ProtoDUNE-SP length data and LV power cables, 4 on the top and 4 on the

27

bottom. Its readout uses the full CE system for ProtoDUNE-SP, with a prototype CE flange

28

and WIEC, 2 WIBs and 1 PTC, as shown in Figure

fig:tpcelec_40APA

1.21. Detailed integration tests of the CE

29

readout performance while following the DUNE grounding and shielding guidelines have been done

30

at the 40% APA. Additional input capacitance (equivalent to longer wire length) have been added

31

to a subset of channels to project the ENC performance from the 40% APA teststand to the

32

ProtoDUNE-SP and SBND detectors. The results from the 40% APA indicate that the full CE

33

system as installed on the teststand at BNL will satisfy the DUNE far detector noise requirements.

34

The cold box at CERN is designed to cycle one full-size DUNE APA with the full compliment of 20

35

FEMB through gaseous Nitrogen temperatures around 150K to check out the APA performance

36

prior to installing the APA into the ProtoDUNE-SP cryostat. It is designed to be a Faraday cage

37

identical to the ProtoDUNE-SP cryostat and is read out by a complete CE system for a single

38

APA, including a CE flange and fully-loaded WIEC with 5 WIBs and 1 PTC.

39

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

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Chapter 1: TPC Electronics 1–32

Figure 1.20: Picture of the shielded room at Fermilab.

fig:shieldedroom

Figure 1.21: Left: one side of the 40% APA with 4 FEMBs. Right: the full CE feedthrough and flange.

fig:tpcelec_40APA

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 40

Chapter 1: TPC Electronics 1–33

1.6 Quality Control

1

sec:fdsp-tpc-elec-qc

This section will be written for the second draft of the technical proposal.

2

1.7 Installation, Integration, and Commissioning

3

sec:fdsp-tpc-elec-install

1.7.1 Installation and Integration with APAs

4

sec:fdsp-tpc-elec-install-apa

The installation and commissioning of the detector components built or purchased by the Cold

5

Electronics (CE) consortium takes place both prior to and after the insertion of the Anode Plane

6

Assemblies (APAs) in the detector cryostat, with testing performed after each step, to avoid the

7

need for rework that could cause significant delays. The installation and initial commissioning of

8

the CE electronics is likely to be on the critical path for the completion of the single phase detector

9

and the amount of time available for testing and possibly repairing / replacing components after

10

their installation is going to be very limited. Cold tests of the complete APAs may not be possible

11

for the entire detector, and this requires that all the CE components are qualified for operation in

12

LAr prior to their installation.

13

After the completion of the cryostat, the chimneys that are house all the cables for the CE, PDS,

14

and HV consortia (with the exception of the high voltage feedthrough for the cathode planes) are

15

installed and leak tested. This also includes the installation of the crossing tube cable support and

16

f the flanges that provide the cold to warm interface for all the cables. In parallel the racks that

17

house the CE and PDS electronics components on the top of the cryostat, and the corresponding

18

CISC and detector safety system monitoring, controlling, and interlock hardware can be installed.

19

Cable trays between different chimneys belonging to a same set of 6 APAs and 2 CPAs can also

20

be put in place. Readout fibre bundles between the chimneys and the central utility cavern used

21

for the readout of the wire information from the APAs can also be put in place. In the meantime

22

inside the cryostat all the cable trays used to support the CE and PDS cables and to accommodate

23

the slack of the cables can be put in place.

24

In parallel the 20 front-end motherboards (FEMBs) required to read out the wires from one APA

25

are installed with their shielding box onto the APA and connected to the CR boards. This work

26

will be performed at the integration facility (or facilities), because there will not be enough space

27

to perform this type of work in parallel on multiple APAs in the detector cavern. Once the FEMBs

28

are installed a temporary set of cables will be used to connect each FEMB to a temporary power,

29

control, and readout system to ensure that all the wires can be properly read-out. For a more

30

thorough set of tests, this set of temporary cables will be connected to warm interface boards

31

(WIBs) housed in a warm interface crate (WIC) identical to the one used in DUNE. The WIBs

32

would then be read out with a DAQ system identical to the one used after the installation of the

33

APAs into the detector cryostat. With this setup all the wires connected to an APA and also the

34

corresponding PDS components can be read out simultaneously, allowing for the investigation and

35

resolution of possible noise and cross talk issues. While it would be desirable to perform these tests

36

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 41

Chapter 1: TPC Electronics 1–34

in a cold box operating at or close to LAr temperature, the tightness of the installation schedule

1

may require that these tests are performed at room temperature for all the APAs. Assuming that

2

all the CE components have already been qualified for operation in LAr, only a sample of the

3

APAs would be tested in cold conditions. Once these tests are completed the temporary cables are

4

disconnected and the APA is prepared for shipment to Sanford Lab. It is not considered feasible

5

to transport the top APA from the integration facility to the detector cryostat with the CE cables

6

already installed. For the bottom APA the final cables can be installed only after the two APAs

7

are mated together in the “toaster" area just outside of the detector cryostat.

8

Further work on the CE components installed on the APAs is performed after the APAs are

9

transported to the clean area outside the cryostat inside Sanford Lab. All the cables that provide

10

power and control and that are used to read out the 20 FEMBs of the top and bottom APAs need

11

to be installed, as well as the cables that connect to the SHV boards that are used to distribute

12

the bias voltage to the APA wires, to the electron diverters, and to the field cage termination

13

electrodes. The cables for the bottom APA need to be routed through the frames of the APAs,

14

an operation that can be performed only after the two APAs are mechanically coupled inside the

15

“toaster" area. Quick tests are performed after the installation of the final cables, and then the

16

APAs can be moved to their final position inside the detector cryostat. At that point the CE and

17

PDS cables can be routed through the chimney and connected to the respective flanges and their

18

strain reliefs. The flanges are then moved to the final position on the chimneys and leak tests and

19

electrical connectivity tests can be performed. Then the bottom plate of the crossing tubes with

20

its additional strain relief for the CE and PDS cables can be put in place, and the final slack of the

21

cables can be arranged in the cable trays attached to the supports inside the cryostat. After the

22

cabling work is completed, the WICs for a pair of APAs can be installed on the chimney and more

23

testing of the entire power, control, and readout chain can be performed, first with local control,

24

and later after connection of the readout and timing and control fibres to the WIBs using the final

25

DAQ system.

26

The current plans foresee that six APAs and two CPAs are installed and tested in one week before

27

moving on to the next set. As soon as another set of APAs and CPAs is in place any replacement

28

f components or rework of connections inside the cryostat becomes very difficult or impossible.

29

This requires that all readout tests are performed very quickly after each step in the installation.

30

The schedule foresees four work days each week for the installation work (in two eight hours shifts).

31

The testing activities may require that work is performed in parallel, i.e. that the CE components

32

f a pair of APAs are tested while another pair is being installed and/or connected to the powering,

33

control, and readout system. It is also likely that the testing work may require a more extended

34

working schedule (six or seven working days per week). More complex tests, involving readout

35

ut multiple rows of APAs, will continue throughout the entire period (8 months) during which

36

all the detector components are installed inside the cryostat. Final tests should be performed

37

reading out the entire detector through the DAQ system prior to the closure of the TCO and

38

before starting filling the cryostat with Ar and cooling down. There will be a hyatus in the

39

commissioning activities during the filling of the cryostat. The commissioning at LAr temperature

40

will be most likely possible only after the cryostat is completely full.

41

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 42

Chapter 1: TPC Electronics 1–35

1.7.2 Calibration

1

sec:fdsp-tpc-elec-install-calib

This section will be written for the second draft of the technical proposal.

2

1.8 Safety

3

sec:fdsp-tpc-elec-safety

The TPC electronics will be built and handled in such a way as to ensure the safety of both

4

personnel and equipment. The team will work closely with the project Technical Coordination

5

rganization to make sure that all applicable safety procedures are followed and documented.

6

The instrumentation of the TPC electronics will include multiple printed circuit boards and cabling.

7

The cabling includes the high voltage wire bias distribution, low voltage power and signals. Each

8

f these elements will require attention to relevant safety standards and solutions will be subject

9

to the review of the project Technical Coordination organization.

10

All printed circuit boards will be designed such that the connectors and copper carrying traces are

11

rated to sustain the maximum current load. In the case of the low voltage warm electronics, all

12

boards will be fused following prescribed safety standards. The cold electronic low voltage boards

13

inside the cryostat will not be fused because these boards will be inaccessible during operations

14

and fire is not a danger once the cryostat is filled with liquid argon. Special precautions should be

15

taken during installation and commissioning of the cold electronics prior to the cryostat being filled

16

with liquid argon. The TPC electronics group will work with the project Technical Coordination

17

to implement this.

18

All cabling and connectors will be selected such that they meet or exceed the possible current

19

ampacity and voltage ratings of the connected power supplies. In the case of high voltage distri-

20

bution, all accessible warm connectors will be SHV type connectors which will limit the possibility

21

f a touch potential which could shock a person. In the cold, many of the high voltage connections

22

will be open soldered connections. Care will be taken that ensures personnel safety should these

23

connections need to be energized while the APA is exposed. However, it is not anticipated that

24

APA wire bias will be powered by more than 50 volts unless the APA is enclosed within a Faraday

25

shield.

26

Finally, the safety of the equipment must be taken into account during production, initial check

27

ut, installation and cabling. Proper electrostatic discharge (ESD) procedures will be followed

28

at all stages, including use of ESD safe bags for storage and ESD wrist straps used by personnel

29

when handling the cards. The TPC electronics will also make use of shorting connectors on all

30

cables which are attached to the printed circuit cards, but not attached at the far end. During

31

installation, multiple long cables will be attached to front end boards, but will not be attached

32

to the connectors on the flanges for some period of time. Detailed procedures for the use of cable

33

shorting connectors will be written and used.

34

Finally, the handling of the APA and attached front end electronics must follow ESD safe handling

35

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 43

Chapter 1: TPC Electronics 1–36

procedures whenever the APA is moved from one ground reference to another, or after it has been

1

left in a “floating” state for any period of time. Whenever the APA is moved and could encounter

2

a step potential, a connection must be made through a slow discharge path which will equalize the

3

APA frame potential to the new environment. Again, ESD safe handling rules will be documented

4

and followed.

5

1.9 Organization and Management

6

sec:fdsp-tpc-elec-org

1.9.1 Single-Phase TPC Electronics Consortium Organization

7

sec:fdsp-tpc-elec-org-consort

For the moment the CE consortium does not have an official substructure with coordinators ap-

8

pointed to oversee specific areas. This is in part due to the current focus on ASIC development:

9

informal subgroups exist that are following the design of the various ASIC. Hucheng Chen (BNL) is

10

leading the design of the new version of LArASIC, and in parallel following the studies of commer-

11

cial ADCs for SBND. Carl Grace (LBNL) is leading the effort of LBNL, BNL, and FNAL, on the

12

design of a new ADC in 65 nm technology. Terry Shaw (FNAL) is overseeing the development of

13

the new COLDATA ASIC, and Angelo Dragone (SLAC) is overseeing the adaptation of the nEXO

14

CRYO ASIC for use in DUNE. A new working group tasked with studying reliability issues in the

15

CE components and preparing recommendations for the choice of ASICs, the design of printed

16

circuit boards, and testing. This working group could form the basis for the group tasked with

17

developing the QA/QC program for the CE detector components and then monitoring it. We plan

18

to reassess the structure of the group in a few months, with a likely split between components

19

inside and outside the cryostat, a group responsible for testing, and contact people for calibration,

20

physics, software and computing, and integration and installation.

21

1.9.2 Planning Assumptions

22

sec:fdsp-tpc-elec-org-assmp

Please note that these dates may need to be revisited and that there may be more time available prior to the beginning of construction.

23

Plans for the CE consortium are based on the overall schedule for DUNE that assumes that the

24

first APAs need to be fully populated with electronics and tested toward the end of 2020. The APA

25

production needs to be completed about 12 months later and the installation in the cryostat should

26

be finished by mid-2022. This defines the time window for the completion of the R&D program on

27

the ASICs: a set of ASICs (or a single ASIC) meeting all the DUNE requirements needs to have

28

been qualified by Fall 2019, such that preproduction ASICs and the corresponding FEMBs can be

29

assembled and tested in Spring 2020, launching the full production in Summer 2020. Meeting this

30

timeline requires that the development of the ASICs, and in particular of the newly designed ones

31

(the SLAC CRYO ASIC, the joint LBNL-BNL-FNAL ADC, and COLDATA) are prototyped by

32

the end of Summer 2018, with testing completed by the end of 2018. This would allow a second

33

round of prototyping, if necessary, in the first half of 2019. The FEMBs used for protoDUNE will

34

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 44

Chapter 1: TPC Electronics 1–37

likely have to be redesigned to house a new ADC and to replace the FPGA used in protoDUNE

1

with the COLDATA ASIC. Multiple variants of this board will be necessary, depending on the

2

success of the various ADC R&D projects being currently pursued. These design changes will be

3

made in the second half of 2018. Additional FEMBs prototypes will be designed and fabricated

4

depending on the outcome of the initial testing of the SLAC CRYO ASIC. A second iteration of

5

FEMB prototype(s) will be necessary in 2019, when the final ASICs (that may have a different

6

channel count from the first prototype) will become available.

7

We assume that for apart from the ASIC, where rapid development is still required, and the

8

FEMBs, which have to be redesigned to accommodate the new ASICs, most of the detector

9

components to be delivered by the CE consortium will require only minor changes relative to the

10

protoDUNE components. For this reason the modifications of these other detector components

11

will be delayed until 2019, which will also help with the availability of funding. Exceptions will

12

be made for further development in test stands, for cabling studies, and for conceptual studies of

13

automated testing assemblies, rack space assignment, and of the interface to the DAQ system.

14

1.9.3 WBS and Responsibilities

15

sec:fdsp-tpc-elec-org-wbs

This section will be written for the second draft of the technical proposal.

16

1.9.4 High-level Cost and Schedule

17

sec:fdsp-tpc-elec-org-cs

This section will be written for the second draft of the technical proposal.

18

23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 45

Chapter 1: TPC Electronics 1–38 23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

SLIDE 46

REFERENCES 1–39

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23 Feb 2018: First draft of the TP volumes due DUNE Technical Proposal

Deep Underground Neutrino Experiment (DUNE)

Technical Proposal

23 Feb 2018: First draft of the TP volumes due

Volume 2: The Single-Phase Far Detector

Contents

List of Figures

List of Tables

Todo list

Chapter 1

TPC Electronics

1.1 System Overview

1.1.1 Introduction

1.1.2 Design Considerations

1.1.3 System Requirements

1.2 System Design

1.2.1 Grounding and Shielding

1.2.2 Distribution of Wire-Bias Voltages

1.2.3 Front-End Mother Board (FEMB)

1.2.4 Additional FEMB/ASIC Designs

1.2.5 Cold Electronics Feedthroughs and Cold Cables

1.2.6 Warm Interface Electronics

1.2.7 External Power and Supplies

1.3 Production and Assembly

1.4 Interfaces

1.4.1 Overview

1.4.2 APAs

1.4.3 DAQ

1.5 Quality Assurance

1.5.1 Initial Design Validation

1.5.2 Integrated Test Facilities

1.6 Quality Control

1.7 Installation, Integration, and Commissioning

1.7.1 Installation and Integration with APAs

1.7.2 Calibration

1.8 Safety

1.9 Organization and Management

1.9.1 Single-Phase TPC Electronics Consortium Organization

1.9.2 Planning Assumptions

1.9.3 WBS and Responsibilities

1.9.4 High-level Cost and Schedule

References