DC and Transient Responses (i.e. delay) (some comments on power - PowerPoint PPT Presentation

DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris)

Outline • Today… – 1st… • Quickly review material from last time – 2nd… • Briefly think about transistor operation in context of logic gates – 3rd… • Use basic logic gates to study trends relating to power & delay in context of device scaling

MOSFET cross section… With applied V gs , depletion region forms n n P

Review: MOS Capacitor • Gate and body form MOS capacitor • Operating modes polysilicon gate V g < 0 silicon dioxide insulator + p-type body - (a) 0 < V g < V t depletion region + - (b) V g > V t inversion region + depletion region - (c)

Review: nMOS Cutoff • No channel formed, so no current flows • I ds = 0 V gs = 0 V gd + g + - - s d n+ n+ p-type body b

Review: nMOS Linear • Channel forms V gs > V t V gd = V gs + g + • Current flows from d to s - - s d – e - from s to d V ds = 0 n+ n+ • I ds increases with V ds p-type body b • Similar to linear resistor V gs > V t V ds = 0, no current V gs > V t V gs > V gd > V t g + + - - d I ds s n+ n+ 0 < V ds < V gs -V t p-type body b V gs > V t V ds > 0, but < (V gs - V t ) (current flows)

Review: nMOS Saturation • Channel pinches off • I ds independent of V ds • We say current saturates • Similar to current source V gs > V t V gd < V t g + + - - d I ds s n+ n+ V ds > V gs -V t p-type body b V ds > V gs - V t Essentially, voltage difference over induced channel fixed at V gs - V (current flows, but saturates) (or i ds no longer a function of V ds )

nMOS I-V Summary • Shockley 1 st order transistor models � 0 V V cutoff � < gs t � V � � � I V V V V V linear ds = � � � < � � � 2 ds gs t ds ds dsat � � � � � 2 ( ) V V V V saturatio n � > � gs t ds dsat 2 �

We’ll start by considering logic gates in the context of transistor currents… (for CMOS-based circuits…)

CMOS Gate Design • 4-input CMOS NOR gate A B Out A B 0 0 1 C 0 1 0 D 1 0 0 Y 1 1 0 (2-input NOR for reference)

Why CMOS? • High noise margins: – Voltage swing ~ = supply voltage • No direct path between supply and ground rails under steady-state operating conditions – (I.e. when input and outputs remain constant) – Absence of current flow = no static power • But this isn’t exactly true as we’ll see… • All early Intel microprocessors NMOS only • (see NMOS inverter at right) • Hard to achieve 0 static power • Put firm upper bound on # of gates Single transistor • Necessitated move to CMOS in 1980s pulls signal low.

1st, DC Response • DC Response: V out vs. V in for a gate • Ex: Inverter – When V in = 0 --> V out = V DD – When V in = V DD --> V out = 0 V DD – In between, V out depends on transistor size and current I dsp V in V out – Want: I dsn = |I dsp | I dsn – We could solve equations – But graphical solution gives more insight

Transistor Operation • Current depends on region of transistor behavior • For what V in and V out are nMOS and pMOS in – Cutoff? – Linear? – Saturation?

nMOS Operation Recall… Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn Same V dsn <V gsn – V tn V dsn >V gsn – V tn V ds <V gs – V t V ds <V gs – V t No Current V DD In inverter context, I dsp what is V gs , V ds V in V out for NMOS device? I dsn

nMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn <V gsn – V tn V dsn >V gsn – V tn V DD V gsn = V in I dsp V in V out V dsn = V out I dsn

nMOS Operation (in context of inverter input V) Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V in < V tn V in > V tn V in > V tn V dsn <V gsn – V tn V dsn >V gsn – V tn V out <V in - V tn V out >V in - V tn V DD V gsn = V in I dsp V in V out V dsn = V out I dsn

pMOS Operation (for reference) Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V in > V DD + V in <V DD + V tp V in <V DD + V tp V tp V dsp >V gsp – V tp V dsp <V gsp – V tp V out >V in - V tp V out <V in - V tp V DD V gsp = V in - V DD V tp < 0 I dsp V in V out V dsp = V out - V DD I dsn

I-V Characteristics • Make pMOS is wider than nMOS such that β n = β p V gsn5 V gsn4 I dsn V gsn3 -V dsp V gsn2 -V DD V gsp1 V gsn1 V gsp2 0 V DD V dsn V gsp3 Can plot I ds as function of V gs , V dd V gsp4 -I dsp (sign conventions from PMOS/NMOS devices) V gsp5

Load Line Analysis • For a given V in : (Translate lines onto same set of axes…) – Plot I dsn , I dsp vs. V out – V out must be where |currents| are equal in (For DC operating point to be valid - consider graphical intersection of load lines… i.e. current in pMOS > current in nMOS V in0 V in5 pMOS nMOS V DD V in1 V in4 I dsn , |I dsp | I dsp V in V out V in2 V in3 I dsn V in3 V in2 V in4 V in1 V DD V out

DC Transfer Curve • Transcribe points onto V in vs. V out plot V DD V in0 V in5 A B V out V in1 V in4 C V in2 V in3 V in3 V in2 D E V in4 V in1 0 V tn V DD /2 V DD +V tp V DD V DD V out V in

Comments: • All operating points are located near high or low output levels • The VTC of the inverter exhibits a very narrow transition zone • This results from high gain during the switching transient – (When both NMOS, PMOS are in saturation and on simultaneously) – (In this region, small change in the input voltage results in a large output variation)

Operating Regions • Revisit transistor operating regions Region nMOS pMOS V DD A Cutoff Linear A B B Saturation Linear V out C C Saturation Saturation D Linear Saturation D E E Linear Cutoff 0 V tn V DD /2 V DD +V tp V DD V in

A few more interesting points…

Beta Ratio • If β p / β n ≠ 1, switching point will move from V DD /2 • Called skewed gate • Other gates: collapse into equivalent inverter V DD � p 10 � = n V out 2 1 0.5 � p 0.1 � = n 0 V DD V in

Noise Margins • How much noise can a gate input see before it does not recognize the input? Output Characteristics Input Characteristics V DD Logical High Logical High V OH Output Range Input Range NM H V IH Indeterminate Region V IL NM L Logical Low Logical Low V OL Input Range Output Range GND

Logic Levels • To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic Acceptable low input to get high output V out Unity Gain Points V DD Slope = -1 V OH � p / � n > 1 V in V out V OL V in 0 V DD - V tn V IL V IH V DD |V tp | Acceptable high input to get low output

Supply voltage scaling • As supply voltage scales down - which can be good as we’ll see - can have problems – To a point (~0.5V), scaling Vdd improves gain – Beyond, DC characteristics become increasingly sensitive to variations in the device parameteres • E.g. transistor threshold – Scaling supply voltages reduces signal swing • Makes design more sensitive to external noise sources that don’t scale.

Next, board discussion on transient response, power.