DC and Transient Responses (i.e. delay) (some comments on power - - PowerPoint PPT Presentation

DC and Transient Responses (i.e. delay) (some comments on power too!)

Michael Niemier (Some slides based on lecture notes by David Harris)

Outline

• Today…

– 1st…

• Quickly review material from last time

– 2nd…

• Briefly think about transistor operation in context of logic

gates

– 3rd…

• Use basic logic gates to study trends relating to power &

delay in context of device scaling

MOSFET cross section…

n P

With applied Vgs, depletion region forms

n

Review: MOS Capacitor

• Gate and body form MOS capacitor
• Operating modes

polysilicon gate (a) silicon dioxide insulator p-type body +

• Vg < 0

(b) +

• 0 < Vg < Vt

depletion region (c) +

• Vg > Vt

depletion region inversion region

Review: nMOS Cutoff

• No channel formed, so no current flows
• Ids = 0

+

• Vgs = 0

n+ n+

+

• Vgd

p-type body b g s d

Review: nMOS Linear

• Channel forms
• Current flows from d to s

– e- from s to d

• Ids increases with Vds
• Similar to linear resistor

+

• Vgs > Vt

n+ n+

+

• Vgd = Vgs

Vds = 0 p-type body b g s d

Vgs > Vt Vds = 0, no current

+

• Vgs > Vt

n+ n+

+

• Vgs > Vgd > Vt

0 < Vds < Vgs-Vt p-type body b g s d Ids

Vgs > Vt Vds > 0, but < (Vgs - Vt) (current flows)

Review: nMOS Saturation

• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source

+

• Vgs > Vt

n+ n+

+

• Vgd < Vt

Vds > Vgs-Vt p-type body b g s d Ids

Vds > Vgs - Vt Essentially, voltage difference over induced channel fixed at Vgs - V (current flows, but saturates) (or ids no longer a function of Vds)

nMOS I-V Summary

( )

2

cutoff linear saturatio 2 2 n

gs t ds ds gs t ds ds dsat gs t ds dsat

V V V I V V V V V V V V V

• <
• =
• <
• >
• Shockley 1st order transistor models

We’ll start by considering logic gates in the context of transistor currents…

(for CMOS-based circuits…)

CMOS Gate Design

• 4-input CMOS NOR gate

A B C D Y

1 1 1 1 1 Out B A (2-input NOR for reference)

Why CMOS?

• High noise margins:

– Voltage swing ~ = supply voltage

• No direct path between supply and ground rails under

steady-state operating conditions

– (I.e. when input and outputs remain constant) – Absence of current flow = no static power

• But this isn’t exactly true as we’ll see…
• All early Intel microprocessors NMOS only
• (see NMOS inverter at right)
• Hard to achieve 0 static power
• Put firm upper bound on # of gates
• Necessitated move to CMOS in 1980s

Single transistor pulls signal low.

1st, DC Response

• DC Response: Vout vs. Vin for a gate
• Ex: Inverter

– When Vin = 0

• ->

Vout = VDD – When Vin = VDD

• ->

Vout = 0 – In between, Vout depends on transistor size and current – Want: Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight Idsn Idsp Vout VDD Vin

Transistor Operation

• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in

– Cutoff? – Linear? – Saturation?

nMOS Operation

Vgsn > Vtn Vdsn>Vgsn – Vtn Vgsn > Vtn Vdsn<Vgsn – Vtn Vgsn < Vtn Saturated Linear Cutoff

Idsn Idsp Vout VDD Vin

Recall…

Same No Current Vds<Vgs – Vt Vds<Vgs – Vt In inverter context, what is Vgs, Vds for NMOS device?

nMOS Operation

Vgsn > Vtn Vdsn>Vgsn – Vtn Vgsn > Vtn Vdsn<Vgsn – Vtn Vgsn < Vtn Saturated Linear Cutoff

Idsn Idsp Vout VDD Vin

Vgsn = Vin Vdsn = Vout

nMOS Operation (in context of inverter input V)

Vgsn > Vtn Vin > Vtn Vdsn>Vgsn – Vtn Vout>Vin - Vtn Vgsn > Vtn Vin > Vtn Vdsn<Vgsn – Vtn Vout<Vin - Vtn Vgsn < Vtn Vin < Vtn Saturated Linear Cutoff

Idsn Idsp Vout VDD Vin

Vgsn = Vin Vdsn = Vout

Vgsp < Vtp Vin<VDD + Vtp Vdsp<Vgsp – Vtp Vout<Vin - Vtp Vgsp < Vtp Vin<VDD + Vtp Vdsp>Vgsp – Vtp Vout>Vin - Vtp Vgsp > Vtp Vin > VDD + Vtp Saturated Linear Cutoff

Idsn Idsp Vout VDD Vin

Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0

pMOS Operation

(for reference)

I-V Characteristics

• Make pMOS is wider than nMOS such that βn = βp

Vgsn5 Vgsn4 Vgsn3 Vgsn2 Vgsn1 Vgsp5 Vgsp4 Vgsp3 Vgsp2 Vgsp1 VDD

• VDD

Vdsn

• Vdsp
• Idsp

Idsn Can plot Ids as function of Vgs, Vdd (sign conventions from PMOS/NMOS devices)

Load Line Analysis

Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD

• For a given Vin:

– Plot Idsn, Idsp vs. Vout – Vout must be where |currents| are equal in

Idsn Idsp Vout VDD Vin (Translate lines onto same set of axes…) i.e. current in pMOS > current in nMOS pMOS nMOS (For DC operating point to be valid - consider graphical intersection of load lines…

DC Transfer Curve

• Transcribe points onto Vin vs. Vout plot

Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Vout VDD C Vout Vin VDD VDD A B D E

Vtn VDD/2 VDD+Vtp

Comments:

• All operating points are located near high or low
• utput levels
• The VTC of the inverter exhibits a very narrow

transition zone

• This results from high gain during the switching

transient

– (When both NMOS, PMOS are in saturation and on simultaneously) – (In this region, small change in the input voltage results in a large output variation)

Operating Regions

• Revisit transistor operating regions

C Vout Vin VDD VDD A B D E

Vtn VDD/2 VDD+Vtp

Cutoff Linear E Saturation Linear D Saturation Saturation C Linear Saturation B Linear Cutoff A pMOS nMOS Region

A few more interesting points…

Beta Ratio

• If βp / βn ≠ 1, switching point will move from VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter

Vout Vin VDD VDD 0.5 1 2

10

p n

• =

0.1

p n

• =

Noise Margins

• How much noise can a gate input see before it does

not recognize the input?

Indeterminate Region NML NMH Input Characteristics Output Characteristics VOH VDD VOL GND VIH VIL Logical High Input Range Logical Low Input Range Logical High Output Range Logical Low Output Range

Logic Levels

• To maximize noise margins, select logic levels at

– unity gain point of DC transfer characteristic

VDD Vin Vout VOH VDD VOL VIL VIH Vtn Unity Gain Points Slope = -1 VDD- |Vtp| p/n > 1 Vin Vout

Acceptable high input to get low output Acceptable low input to get high output

Supply voltage scaling

• As supply voltage scales down - which can be good as

we’ll see - can have problems

– To a point (~0.5V), scaling Vdd improves gain – Beyond, DC characteristics become increasingly sensitive to variations in the device parameteres

• E.g. transistor threshold

– Scaling supply voltages reduces signal swing

• Makes design more sensitive to external noise sources that

don’t scale.

Next, board discussion on transient response, power.