SLIDE 1
Data Acquisition System of the PAMELA Experiment
INFN Roma II, Università di Roma “Tor Vergata” Alessandro Basili
Florence Naples Trieste Rome CNR, Florence Siegen KTH, Stockholm
Data Acquisition System of the PAMELA Experiment Alessandro Basili - - PowerPoint PPT Presentation
Data Acquisition System of the PAMELA Experiment Alessandro Basili - - PowerPoint PPT Presentation
Florence KTH, Stockholm Trieste Rome CNR, Florence Siegen Naples Data Acquisition System of the PAMELA Experiment Alessandro Basili INFN Roma II, Universit di Roma Tor Vergata Presentation Overview 1) The acquisition strategy:
SLIDE 2
SLIDE 3
Requirements & constraints
Trigger rate estimation:
- S1 x S2 x S3
12 Hz / G.F. = 20.5 cm2sr Packet size per event: 6 KBytes (roughly), more then 40,000 analog channels
6 GByte per day
6 downloads per day 200 seconds connection speed rate of 12 MBps
SLIDE 4
Data reduction solution
Front end boards DSP boards IDAQ board PSCU Trigger board
A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D IDAQ IDAQ PSCU Tracker Calorimeter Tof AC DSP DSP DSP DSP ND S4 DSP DSP DSP DSP Trigger board
SLIDE 5
Trigger-busy mechanism
Trigger board sends trigger to every
- ne, only if the idaq busy signal is
released. Idaq starts in busy condition. Only at the end of settings configurations will be sent a “release busy” command
Power on PSCU Idaq Trigger
S1 S2 S3
busy trigger
Trigger vetoed Trigger delivered
SLIDE 6
PSCU-IDAQ protocol
1) Settings before the acquisition: 2) DMA arming: 3) Acquisition runs: cycled reloading of the command queue
- Trigger mode
- calibration
- initialization
- Command queue selection
- Event header written in the Ram
- Data timeout and Event timeout fixed
Important: the cpu time consuming is very low; the acquisition is managed by the IDAQ (no interrupt handling)
SLIDE 7
Event acquisition overview
1) Pamela starts up: the Idaq is busy 2) First command is sent: RELEASE BUSY 3) First trigger comes and Idaq goes again in “busy” state. 4) The read commands are hanging on because idaq will release the acknoledge to the PIF only after 3.5 ms from the trigger 5) All the “read event” commands are sent to all subdetectors 6) Once the whole data are stored in PIF Ram, the “DATA TIMEOUT” interrupt will tell the cpu that the acquisition has finished.
PSCU IDAQ
Not busy
FE FE FE
SLIDE 8
Event acquisition overview
Idaq busy cmd strb cmd ack daq strb daq ack Idaq trigger
3.5 ms timeout: for compression algorithm
Commands to DSP boards Answers from DSP boards Vetoed triggers
SLIDE 9
IDAQ : interface data acquisition
CMD Buffer
SRAM 512Kx8 ADSP2187 TX Mux 1 in - 14 out RX Mux 14 in - 1 out
IN-Buffers OUT-Buffers
TTL TTL LVDS LVDS
DSP controller e checker PM & DM FLASH 1Mx8 RAM CTRL con Hamming codec
LVDS LVDS TTL
DAQ Buffer
TTL
Async interfaces RS 422
SRAM 512Kx8 FLASH 1Mx8 FLASH CTRL con Hamming codec MAIN controller e multiplexer
LVDS
TRIGG BUSY
RS 422
RESET ALARM
Status & PWR
SLIDE 10
IDAQ : interface data acquisition Ram controller
SERIAL Interface HAMMING tx end_tx rx end_cmd RAMRES cmd_nda MCLK RAM_ERR cmd_err A[17..0] D[7..0] WEN OEN CEN BHE BLE AR[17..0] DR[7..0] WERN OERN CERN BHER BLER clk_tx RAMSERCLK RAM Interface DEC_CMD
SLIDE 11
IDAQ : interface data acquisition Flash controller
SERIAL Interface HAMMING tx end_tx rx end_cmd FLASHRES busy MCLK Hamm_err cmd_err AH [19..0] DH [7..0] WEN_H OEN_H CEN_H RYBYN_H RESETN_H AL [19..0] DL [7..0] clk_tx FLASHSERCLK FLASH Interface DEC_CMD WEN_L OEN_L CEN_L RYBYN_L RESETN_L
SLIDE 12
IDAQ : interface data acquisition DSP controller
SERIAL Interface tx end_tx rx end_cmd DSPRES busy MCLK dat_err cmd_err nIAD [15..0] clk_tx DSPSERCLK IDMA Interface DEC_CMD dsp_err checking cmd_nda nIS nIWR nIAL nIRD nIACK nRESET nIRQL0 nPWD FL0 FL1 FL2 PF4 PF6 PF7 CLKIN mode [3..0]
SLIDE 13
PSCU
CPU HKU PIF 32 32 Mem Mod DC/DC
Sys BUS PCMCIA BUS W BUS R BUS
CMD DAT TAM TC TM 1553 MIL STD
SLIDE 14
CPU module
1) Processor SPARC32 V7 2) SRAM 1M x 32 EDAC protected 3) Boot PROM 17 Mips @24 MHz JTAG provided
SLIDE 15
CPU module
4) EEPROM 256K x 32 EDAC protected 5) MIL-STD 1553 Bus Controller/Remote Terminal Function with 64K x 16 Ram buffer 6) CRIMEA: glue logic for PCMCIA bus controller, parallel S-90 bus interface
SLIDE 16
SSMM module
1) Eleven indipendent memory columns 2) Each column is composed by 4 Memory Cubes 3) Each Cube is 8 x 8 MB chip SDRAM 8 modules for data storage, 2 for Reed- Solomon Check Symbols and 1 for local redundancy 4) Eleven indipendent Current Limiter for Latch-up protection 5) DRAMMA: Asic for DRAM managing
SLIDE 17
PIF module
FPGA based interface (ALVARO): 1) CMD DMA management 2) DAQ DMA management 3) MM Parallel W/R bus management 4) TAM DMA management 5) 1 programmable Event Timeout 6) 1 programmable Data Timeout
SLIDE 18
HKU module
House keeping unit: FPGA based interface 1) 2 serial links RS422 2) 24 High voltage commands (26 V) 3) 2 Differential Bi-level commands 1) 32 Contact closures 2) 8 Bi-level acquisition
commands
3) 4 Differential Bi-level acquisition 4) 16 Analog double ended acquisition 5) 16 Analog double ended thermistors 6) 2 Serial Digital 16 bits acquisition
acquisitions
SLIDE 19