CSE140: Components and Design Techniques for Digital Systems - PowerPoint PPT Presentation

CSE140: Components and Design Techniques for Digital Systems Register Transfer Level (RTL) Design Slides from Tajana Simunic Rosing Sources: TSR, Katz, Boriello, Vahid, Perkowski

CAPE Please submit your evaluations !!!! Sources: TSR, Katz, Boriello, Vahid, Perkowski

About the final ~150 minutes Final Exam Problems including (but not limited to): - ALU design - ALU components (shifters, adders, etc.) - FSM - Moore, Mealy, design of FSM using state table, excitation table - Timing constraints - RTL design and HLSM You can have a cheat sheet with you, but nothing else Sources: TSR, Katz, Boriello, Vahid, Perkowski

Topics for today • Another example of RTL design • RTL circuit delays and clock • HLSM array and Register Files • HLSM and C-code • Data-dominated Vs Control-dominated RTL design Sources: TSR, Katz, Boriello, Vahid, Perkowski

Example of RTL design • Use the RTL design process to design a system that outputs the product (P) between: • The most recent sample of data input A. • The most recent sample of data input B. • And the ratio (R) between: • The most recent sample of data input A. • The previous most recent sample of data input B. • The system has two 8-bit unsigned data input A and B and two 8-bit unsigned outputs P and R. • The data inputs are sampled when a single bit input S changes from 1 to 0. As long as S is 0, the system keeps on sampling new data and calculating P. • When S changes to 1 again, in addition the system computes and outputs R for a single clock cycle. • Choose the internal bitwidths that prevent overflow. Sources: TSR, Katz, Boriello, Vahid, Perkowski

1: HLSM diagram Input: A (8-bit), B (8-bit), S (1-bit) Output: P (8-bit), R (8-bit) Local registers: Acurr (8-bit), Bcurr (8-bit), Bprev (8-bit), Pout (16-bit), Rout (8-bit) S’ S’ Acurr := A Bcurr := B Init Wait Sample Bprev := Bcurr Pout := Acurr * Bcurr Acurr := 0 S Bcurr := 0 Bprev := 0 Pout := 0 Acurr := A S Rout := 0 Bcurr := B Wait2 Bprev := Bcurr Pout := Acurr * Bcurr Rout := Acurr / Bprev Sources: TSR, Katz, Boriello, Vahid, Perkowski

2.a: Datapath A B ld1 Acurr Bcurr Bprev clr1 // applied to Acurr, Bcurr and Bprev Multiplier Divider ld2 ld1 clr1 Pout Rout clr1 Sources: TSR, Katz, Boriello, Vahid, Perkowski

2.b: Connect datapath and controller A B ld2 S ld1 clr1 Datapath Controller P R Sources: TSR, Katz, Boriello, Vahid, Perkowski

2.c: Controller FSM S’ Ld1 = 0 Ld2 = 0 Clr1 = 0 S’ Ld1 = 1 Clr1 = 0 Init Wait Sample Clr1 = 1 S S Wait2 Ld1 = 1 Ld2 = 1 Clr1 = 0 Sources: TSR, Katz, Boriello, Vahid, Perkowski

Remember the Soda HLSM? Inputs: c (bit), a(8 bits), s (8 bits) s a Outputs : d (bit) tot_lt_s tot_clr 8 8 Local registers: tot (8 bits) tot_ld s1 s0 c n1 n0 d 0 0 0 0 0 1 0 0 1 c 0 0 0 1 0 1 0 0 1 Add Init 0 0 1 0 0 1 0 0 1 c 0 0 1 1 0 1 0 0 1 Init Wait 0 1 0 0 1 1 0 0 0 tot= tot+a 0 1 0 1 0 1 0 0 0 d Wait tot_ld c ‘ * (tot<s) 0 1 1 0 1 0 0 0 0 Controller Datapath d=0 c ‘ (tot<s) 0 1 1 1 1 0 0 0 0 ‘ tot_clr tot=0 1 0 0 0 0 1 0 1 0 Add Disp 1 1 0 0 0 0 1 0 0 Disp tot_lt_s d=1 s a Inputs: :c,tot_lt_s (bit) tot_ld ld Outputs: d,tot_ld ,tot_clr(bit) clr tpt tot_clr tot_ld 8 c 8 8 c Add tot_clr tot_lt_s 8-bit 8-bit d Init W ait adder < tot_ld=1 tot_lt_s 8 Datapath c ’ * tot_lt_s d=0 tot_clr=1 Disp d=1 Controller Sources: TSR, Katz, Boriello, Vahid, Perkowski

RTL Delay: A Circuit May Have Numerous Paths • Frequency is limited s a by longest register- Combinational logic 8 8 to-register delay d – critical path tot_ld ld • Paths can exist tot tot_clr c – In the datapath clr 8 (c) – In the controller tot_lt_s n1 – Between the controller and 8-bit 8-bit n0 < adder datapath 8 tot_lt_s – May be hundreds Datapath a or thousands of s1 s0 (b) (a) paths clk State register 11 Sources: TSR, Katz, Boriello, Vahid, Perkowski

More Datapath Examples X Y Z X Z X Y Z X Y k=0: Preg = Y + Z k Preg = X + Y + Z Preg = Preg + X Preg=X+Y; regQ=Y+Z k=1: Preg = X + Y Preg Preg Preg regQ Preg P P P Q P (a) (b) (c) (d) Z X Y X Y Z X Y Z X DP DP A B add1 A B A B A B S add1 A B A B add1 add2 add1 add2 S S S S S X + Y A B I I 1 I 0 0 clr I add2 0 I 0 clr clr ld Preg mux2x1 1 ld regQ S ld Preg 1 s0 1 k Q Q Q Q a X + Y + Z I 0 I clr 0 clr Q P P ld Preg 1 1 ld Preg Q Q DP DP P P 12 Sources: TSR, Katz, Boriello, Vahid, Perkowski

ArrayEx Inputs : (none) HLSM Array Example Outputs : P (11 bits) Local storage : A[4](11 bits) Preg (11 bits) Preg := 0 Init1 A[0] := 9 (A[0] == 8)' a Init2 A[1] := 12 12 9 11 11 A[0] == 8 I 1 I 0 Amux A_s s0 Out1 Preg := A[1] Q 8 (a) A_Wa0 W_aW_d A_Wa1 A_We W_e A B ArrayEx Inputs : A_eq_8 A A_Ra0 Acmp Outputs : A_s, A_Wa0, ... RF[4](11) R_a A_Ra1 lt eq gt A_Re Preg_clr = 1 R_e A_s = 0 R_d Init1 A_Wa1=0, A_Wa0=0 A_We = 1 A_eq_8 (A_eq_8)' Preg_clr I clr A_s = 1 ld Preg Init2 A_Wa1=0, A_Wa0=1 Preg_ld Q A_We = 1 DP A_Ra1=0, A_Ra0=0 A_eq_8 (b) A_Re = 1 11 P Out1 Preg_ld = 1 Controller 13 (c) Sources: TSR, Katz, Boriello, Vahid, Perkowski a

BREAK ! Sources: TSR, Katz, Boriello, Vahid, Perkowski

RTL Example: Video Compression Only difference: ball moving Frame 1 Frame 2 Frame 1 Frame 2 Digitized Digitized Digitized Difference of frame 1 frame 2 frame 1 2 from 1 1 Mbyte 1 Mbyte 1 Mbyte 0.01 Mbyte (a) (b) Just send • Video is a series of frames (e.g., 30 per second) difference • Most frames similar to previous frame – Compression idea: just send difference from previous frame Sources: TSR, Katz, Boriello, Vahid, Perkowski

Video Compression – Sum of Absolute Differences compare Each is a pixel, assume Frame 1 Frame 2 represented as 1 byte (actually, a color picture might have 3 bytes per pixel, for intensity of red, green, and blue components of pixel) • If two frames are similar just send a difference instead – Compare corresponding 16x16 “blocks” • Treat 16x16 block as 256-byte array – Compute the absolute value of the difference of each array item – Sum the differences • If above a threshold, send a complete frame for second frame • Else send the difference Sources: TSR, Katz, Boriello, Vahid, Perkowski

Sum-of-Absolute Differences: High-level FSM SAD A Inputs: A, B (256 byte memory); go (bit) Outputs: sad (32 bits) Local registers: sum, sad_reg (32 bits); i (9 bits) B sad go !go S0 go sum = 0 a S1 i = 0 • S0 : wait for go (i<256)’ • S1 : initialize sum and index S2 • S2 : check if done ( i>=256 ) i<256 sum=sum+abs(A[i]-B[i]) S3 • S3 : add difference to sum , i=i+1 increment index sad_reg = sum S4 • S4 : done, write to output sad_reg Sources: TSR, Katz, Boriello, Vahid, Perkowski

Sum-of-Absolute Differences: Datapath AB_addr A_data B_data Inputs: A, B (256 byte memory); go (bit) Outputs: sad (32 bits) Local registers: sum, sad_reg (32 bits); i (9 bits) i_lt_256 <256 8 8 9 i_inc !go S0 – i go i_clr sum = 0 8 S1 i = 0 sum_ld 32 (i<256)’ abs sum S2 sum_clr 8 i<256 32 32 sum=sum+abs(A[i]-B[i]) sad_reg_ld S3 i=i+1 + sad_reg !(i<256) (i_lt_256) sad_reg=sum S4 32 Datapath sad Sources: TSR, Katz, Boriello, Vahid, Perkowski

Sum-of-Absolute Differences: Connect datapath and controller & specify the controller FSM AB_addr A_data B_data go AB_ rd i_lt_256 <256 8 8 go’ S0 9 i_inc go – i sum=0 sum_clr=1 S1 i_clr i=0 i_clr=1 8 sum_ld S2 ? 32 sum abs i<256 i_lt_256 sum_clr sum=sum+abs(A[i]-B[i]) S3 8 sum_ld=1; AB_rd=1 32 32 i=i+1 i_inc=1 sad_reg_ld + S4 sad_reg=sum sad_reg sad_reg_ld=1 32 Controller sad Sources: TSR, Katz, Boriello, Vahid, Perkowski

Behavioral Level Design: C to Gates • Earlier sum-of-absolute-differences example – Started with high-level state machine – C code is an even better starting point -- easier to understand Inputs : A, B [256](8 bits); go (bit) C code Outputs : sad (32 bits) Local storage : sum, sadreg (32 bits); i (9 bits) int SAD (byte A[256], byte B[256]) // not quite C syntax { S0 !go uint sum; short uint I; go sum = 0; sum := 0 S1 i := 0 i = 0; while (i < 256) { sum = sum + abs(A[i] – B[i]); S2 i = i + 1; (i<256)’ i<256 sum:=sum+abs(A[i]-B[i]) } S3 i := i + 1 return sum; } a sadreg := sum S4 Sources: TSR, Katz, Boriello, Vahid, Perkowski

Converting from C to High-Level State Machine • Convert each C construct to equivalent states and transitions • Assignment statement target := target = expression; expression – Becomes one state with assignment • If-then statement – Becomes state with condition check, cond’ transitioning to “then” statements if cond condition true, otherwise to ending if (cond) { (then stmts) // then stmts state } • “then” statements would also be (end) converted to states Sources: TSR, Katz, Boriello, Vahid, Perkowski