CSE 140 Discussion Session 1 Decoder A digital module that - PowerPoint PPT Presentation

CSE 140 Discussion Session 1

Decoder A digital module that converts a binary address to the assertion of the addressed device EN (enable) y 0 0 I 0 0 y 1 1 2 . 1 I 1 3 . 4 5 I 2 2 6 y 7 7 n to 2 n decoder 2 n outputs n inputs function: 2 3 = 8 n= 3 y i = 1 if En= 1 & (I 2, I 1, I 0 ) = i y i = 0 otherwise 2

Decoder • N inputs, 2 N outputs • One-hot outputs: only one output HIGH at once EN 2:4 Decoder 11 Y 3 A 1 Y 2 10 A 0 01 Y 1 00 Y 0 EN= 1 A 1 A 0 Y 3 Y 2 Y 1 Y 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 3

Multiplexer A digital module that selects one of data inputs according to the binary address of the selector. En Description If En = 1 y = D i where i = (S n-1 , .. , S 0 ) D 2n-1 -D 0 Else y y = 0 (Data input) S n-1,0 (Selector) 4

Multiplexer • Selects between one of N inputs to connect to the output. • log 2 N -bit select input – control input S • Example: 2:1 Mux D 0 0 Y D 1 1 S D 1 D 0 Y S Y 0 0 0 0 0 D 0 0 0 1 1 1 D 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 5

Multiplexer Definition: Example En If D 0 = 0 and S 1 S 0 = 00 => y = 0 D 0 0 If D 0 = 1 and S 1 S 0 = 00 => y = 1 D 1 1 y D 2 2 D 3 3 S 1 S 0 6

Multiplexer Example 1: Given f (a,b,c) = S m(0,1,7) + S d(2), implement with an 8-input Mux. En Id a b c f 1 0 1 1 0 0 0 0 1 0 2 0 1 0 0 1 1 3 y 0 4 2 0 1 0 X 0 5 3 0 1 1 0 6 0 7 1 4 1 0 0 0 S 2 S 1 S 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 a b c 7

Multiplexer Example 2: Given f (a,b,c) = S m(0,1,7) + S d(2), implement with 2-input Muxes. a 00 01 10 11 D (b,c) En 0 1 1 X 0 D 0 (b,c) 1 0 0 0 1 D 1 (b,c) En b’ KMAP 0 KMAP y D 0 (b,c ) = b’ D 1 (b,c) = bc 0 1 0 1 X 0 0 c 1 c c 1 0 0 1 a b b b D 1 (b,c) b c = 0 c = 1 0 0 0 l 1 (0) = 0 1 0 1 l 1 (c) = c 8

Multiplexer Example 3: Given f (a,b,c,d) = S m(0,2,4,6,8,9,10,13) + S d(3, 7, 12), implement with 2-input Muxes. bcd Id a b c d f a 000 001 010 011 100 101 110 111 L (b,c,d) 0 0 0 0 0 1 0 1 0 1 X 1 0 1 X L 0 (b,c,d) 1 0 0 0 1 0 1 1 1 1 0 X 1 0 0 L 1 (b,c,d) 2 0 0 1 0 1 3 0 0 1 1 X KMAP cd 00 01 11 10 4 0 1 0 0 1 b 5 0 1 0 1 0 1 0 X 1 0 L0(b,c,d) = d’ 6 0 1 1 0 1 7 0 1 1 1 X 1 0 X 1 1 8 1 0 0 0 1 cd 00 01 11 10 9 1 0 0 1 1 b 10 1 0 1 0 1 0 1 1 1 0 L1(b,c,d) = c’+b’d’ 11 1 0 1 1 0 12 1 1 0 0 X 0 0 X 1 1 13 1 1 0 1 1 14 1 1 1 0 0 9 15 1 1 1 1 0

Multiplexer Example 3 (continued): cd b 00 01 10 11 M (c,d) En En 0 1 1 1 0 M 0 (c,d) 1 X 1 0 0 M 1 (c,d) 1 d’ En y L0 N0 KMAP KMAP d’ M 0 (c,d) = c’+d’ M 1 (c,d) = c’ c’+d’ N1 c’+b’d’ L1 M0 1 1 X 1 c’ M1 c c c 1 0 0 0 a d d b M 0 (c, d) c d = 0 d = 1 N (d) 0 1 1 N 0 (0) = 1 N 1 (c) = d’ 1 1 0 10

Decoder Example 1: Given f (a,b,c,d) = S m(0,2,4,6,8,9,10,13) + S d(3, 7, 12), implement the function using 2:4 decoders and OR gates c EN 0 y0 1 y1 d y2 2 y3 3 c a EN 0 EN 0 y4 y0 y5 y2 1 1 d y6 y4 f 2 b y7 y6 2 3 y8 3 y9 y10 y13 c EN 0 y8 y9 1 d y10 2 3 y11 c y12 EN 0 y13 1 d y14 2 y15 3 11