CSE 140 Discussion Session 1 Decoder A digital module that - - PowerPoint PPT Presentation

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CSE 140 Discussion Session 1 Decoder A digital module that converts a binary address to the assertion of the addressed device EN (enable) y 0 0 I 0 0 y 1 1 2 . 1 I 1 3 . 4 5 I 2 2 6 y 7 7 n to 2 n decoder 2 n outputs n inputs

SLIDE 1

CSE 140 Discussion Session

SLIDE 2

Decoder A digital module that converts a binary address to the assertion of the addressed device

y0 y1 y7

I0 I1 I2 1 2

1 2 3 4 5 6 7

EN (enable) n inputs n= 3 2n outputs 23= 8

yi = 1 if En= 1 & (I2, I1, I0 ) = i yi= 0 otherwise n to 2n decoder function:

. .

SLIDE 3

N inputs, 2N outputs
One-hot outputs: only one output HIGH at once

Decoder

2:4 Decoder A1 A0 Y3 Y2 Y1 Y0 00 01 10 11 1 1 1 1 1 Y3 Y2 Y1 Y0 A0 A1 1 1 1

EN EN= 1

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Multiplexer A digital module that selects one of data inputs according to the binary address of the selector.

Description If En = 1 y = Di where i = (Sn-1, .. , S0) Else y = 0 En y D2n-1-D0 (Data input) Sn-1,0 (Selector)

SLIDE 5

Multiplexer

Selects between one of N inputs to

connect to the output.

log2N-bit select input – control input
Example: 2:1 Mux

Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S D0 Y D1 D1 D0 S Y 1 D1 D0 S

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Multiplexer Definition: Example

En y S1 S0 D0 D1 D2 D3 1 2 3

If D0 = 0 and S1S0 = 00 => y = 0 If D0 = 1 and S1S0 = 00 => y = 1

SLIDE 7

Multiplexer

Example 1: Given f (a,b,c) = Sm(0,1,7) + Sd(2), implement with an 8-input Mux.

Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 X 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 En

y

1 1 1

a b c

S2 S1 S0

1 2 3 4 5 6 7 7

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a 1 00 01 10 11 1 1 X 0 0 0 0 1 D (b,c) D0 (b,c) D1 (b,c) D1 (b,c) b 1 c = 0 c = 1 1 l1(0) = 0 l1(c) = c

En En b’

1 a b

y

c

D0 (b,c) = b’ D1 (b,c) = bc 1 X 1 0 c b 0 0 0 1 c b

Multiplexer Example 2: Given f (a,b,c) = Sm(0,1,7) + Sd(2), implement with 2-input Muxes.

8 KMAP KMAP

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Multiplexer Example 3: Given f (a,b,c,d) = Sm(0,2,4,6,8,9,10,13) + Sd(3, 7, 12), implement with 2-input Muxes.

Id a b c d f 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 1 3 0 0 1 1 X 4 0 1 0 0 1 5 0 1 0 1 0 6 0 1 1 0 1 7 0 1 1 1 X 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 0 12 1 1 0 0 X 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 1 0 a 1 000 001 010 011 100 101 110 111 1 0 1 X 1 0 1 X 1 1 1 0 X 1 0 0 L (b,c,d) L0 (b,c,d) L1 (b,c,d) bcd 1 1 0 X 1 X 1 b 1 cd 00 01 11 10 L0(b,c,d) = d’ 1 1 X 1 0 1 0 0 cd 00 01 11 10 b 1 L1(b,c,d) = c’+b’d’

KMAP

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b 1 00 01 10 11 1 1 1 0 X 1 0 0 M (c,d) M0 (c,d) M1 (c,d) M0 (c, d) c 1 d = 0 1 1 d = 1 1 N (d) N0(0) = 1 N1(c) = d’

En En

d’

L0 L1 a b

y

M0 M1

c’

M0 (c,d) = c’+d’ M1 (c,d) = c’ 1 1 1 0 c d X 1 0 0 c d

Multiplexer Example 3 (continued):

cd c

c’+b’d’ c’+d’

N0 N1

1 d’

En

KMAP KMAP

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Decoder Example 1: Given f (a,b,c,d) = Sm(0,2,4,6,8,9,10,13) + Sd(3, 7, 12), implement the function using 2:4 decoders and OR gates a b

EN EN EN EN EN

c d c c c d d d

y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 y0 y2 y4 y6 y8 y9 y10 y13