CS137: Today Electronic Design Automation Idea Challenges - PDF document

CS137: Today Electronic Design Automation • Idea • Challenges – Path Selection – Victimization – Allocation Day 2: January 6, 2006 • Methodology • Quality, Timing Spatial Routing • Parallelism • Mesh • FPGA Implementation 1 2 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon CS137a: Day22 Global/Detail Pathfinder Review • With limited switching ( e.g. FPGA) • Key step: find-shortest path from src to – can represent routing graph exactly sink – Mark links by usage – Used links cost most – Shortest path tries to avoid • Negotiated Congestion w/ History – Increase cost of congested nodes – Adaptive cost … makes historically congest nodes expensive, try to avoid 3 4 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Slow? Parallelism? • Why is routing slow? • Search all paths in parallel for a single route – Each route: • search all possible paths from source to sink • Search routes for multiple nets in • Number of paths expands as distance 2 parallel • Graph of network is MBs large – Don’t overlap – Large complicated data structure to walk – Overlap? – Won’t all fit in cache – Number of nets = Number of edges – Perform many iterations to converge 5 6 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon 1

Initial Key Ideas Hardware Route Search in Action • Augment existing static network structure to route itself • Use hardware to exploit parallelism in routing 2 – Search all paths in parallel – Route multiple nets in parallel – Avoid walking irregular graph – Specialized/pipelined hardware at each switch • Hardware can perform a route trial 4 in 10s of cycles vs. 10K-100K 7 8 cycles for software CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Path Search Hardware Path Search Hardware Idea • Existing paths already allocated • Drive a one into search paths • All free paths pass up 9 10 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Challenges Select Among Paths? • How select among paths? • Easy: Randomly • What if there are no free paths? – Use PRNG at xover switchbox • Otherwise, need to represent costs… • Can we work without Pathfinder’s history? • How handle fanout? • How handle allocation and victimization? 11 12 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon 2

No Paths? CountNet vs. CountCost • Try stealing a path (rip-up) � victimize existing path • Which one? – Randomly select victim – History-free Pathfinder suggest: • CountCost: 6 • one with least nets shared with other routes � CountCost • CountNetCost: 1 – CountNet: one which intersects least existing nets 13 14 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Implement Counting? CountNet Approximation • Keeping track of which net uses a switch would be much more state/complicated • Approximate CountNet by only delaying at Idea: Delay congested signal conflicting switches Free paths not delayed. Least congested signal arrives at xover first. 15 16 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Implement CounNet Cost is max of sides Approximation • Also note: – Actual cost is max(src � xover,sink � xover) instead of sum Allow to pass if agrees with switch setting. 17 18 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon 3

Algorithm Comparison – Random Netlist How Improve? Total Channels 1100 • Apologize for lack of history? 1000 900 – Exploit fast 800 – Try multiple starts and exploit randomness 700 – Like multiple starts of FM Pathfinder 600 Random 500 400 8 6 2 4 8 6 2 4 8 6 2 4 1 3 6 2 5 1 8 2 4 9 9 1 2 5 0 0 0 1 3 1 2 4 8 6 1 HSRA Array Size 19 20 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Trading Routing Time for Choosing the Right Victims Quality 10 CountCongestion 10 9 CountNet Pathfinder Pathfinder Random Average 8 9 CountNetApproximation Random Best of 20 Quality CountNet # of tracks 7 8 6 7 5 6 4 8 16 32 64 128 256 512 1024 2048 4096 5 8 16 32 64 128 256 512 1024 2048 4096 Array Size Array Size 21 22 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Hypergraphs (Fanout) CountNet • Sequentially route each two-point net, trying to re- use as much as possible from existing allocated paths. 23 24 CountNet � best of 20 starts. CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon 4

Hypergraphs (Fanout) Hypergraphs (Fanout) • Sequentially route each two-point net, trying to re- • Sequentially route each two-point net, trying to re- use as much as possible from existing allocated use as much as possible from existing allocated paths. paths. 25 26 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Hypergraphs (Fanout) Hypergraphs (Fanout) • Sequentially route each two-point net, trying to re- • Sequentially route each two-point net, trying to re- use as much as possible from existing allocated use as much as possible from existing allocated paths. paths. • Add a state bit at every switch – Set when allocate during the current net search. – Clear when we begin to route a new net • Order the destinations associated with a single source • For each destination, – Search from sink as before (only from sink) – At the switch, if the state bit is set and the sink side is congestion free, we have found an available path. – Otherwise, drive ones into all available source paths 27 28 CALTECH CS137 Winter2006 -- DeHon and allocate a new path, like a standard route search. CALTECH CS137 Winter2006 -- DeHon Hypergraphs (Fanout) High Fanout Nets • Sequentially route each two-point net, trying to re- use as much as possible from existing allocated paths. • Victimizing high fanout net will cause • Add a state bit at every switch considerable re-route work – Set when allocate during the current net search. • Might want to penalize victimizing high fanout – Clear when we begin to route a new net nets • Order the destinations associated with a single • CountNetFanout? source – Requires more state…expensive… • For each destination, • Simple hack: lock high fanout nets against – Search from sink as before (only from sink) victimization – At the switch, if the state bit is set and the sink side is congestion free, we have found an available path. – What’s a high fanout net? >10? – Otherwise, drive ones into all available source paths 29 30 CALTECH CS137 Winter2006 -- DeHon and allocate a new path, like a standard route search. CALTECH CS137 Winter2006 -- DeHon 5

Toronto20 − Quality So far Pathfinder CountNet ex5p 10 11.00 alu4 10 10.00 frisc 10 10.45 apex2 11 10.12 misex3 11 10.00 • All Quality apex4 11 11.00 pdc 12 12.00 – …haven’t dealt with all performance details 9 8.01 9 9.06 bigkey s298 • Had basis for confidence in clma 11 11.00 s38417 9 10.00 performance des 9 10.00 s38584 9 9.00 • Wanted to make sure worthwhile first diffeq 8 9.84 seq 11 10.00 dsip 9 8.10 spla 12 12.11 elliptic 10 10.00 tseng 8 10.00 ex1010 10 12.80 Total 199 204.50 31 32 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Hardware Allocation With Victimization Add all nets to R Add all nets to R While nets in R > 0 and routeTrial < RT max While nets in R > 0 and routeTrial < RT max For each unrouted net For each unrouted net Find all possible routes Find all possible routes If found possible routes If found possible routes Randomly select and Randomly select and allocate a route allocate a route Else Else Randomly select a route Select a route to victimize to victimize and allocate and allocate the route the route Endfor Endfor Adjust R Adjust R Endwhile Endwhile Idea: send one down selected path 33 34 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Analysis Methodology Timing Models • Sequential version that does effectively • Hardware Timing the same thing (perhaps inefficiently) – Tpath = length of path ~= log(N) • Count key operations/variables – Tallocate~=Tpath – Number of net searches – Tvictim~=4*Tpath – Number of victims • Software Timing • Timing model for key operations – Tallocate~=Npathsw*(Tm+Tc+Twb+Ta) – Tvictim~=Npathsw*(Tm+Tc)+V*Talloc • Calculate Performance under various • Tm=main memory ref timing assumptions • Tc=cache ref; Twb=write buffer; Ta=bit alloc 35 36 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon 6

Route Time Raw Data N try – number of route starts N RT – number of path searches N RO – number of rip ups N FO – number of fanout searches N FOA – number of fanout allocations 37 38 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon Making comparisons • There is a quality/time tradeoffs • Want to compare at iso-quality 39 40 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon More Parallelism • Only exploiting parallelism in path search • Subtrees are independent • Route root • Then route next two channels in parallel • Then route next 4… 41 42 CALTECH CS137 Winter2006 -- DeHon CALTECH CS137 Winter2006 -- DeHon 7