Context Embedded systems are becoming more complex every day: more - - PDF document

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Context Embedded systems are becoming more complex every day: more - - PDF document

Dec 26, 2022 326 likes •385 views

Context Embedded systems are becoming more complex every day: more functions Giorgio Buttazzo g.buttazzo@sssup.it higher performance higher efficiency new hardware platforms Scuola Superiore SantAnna 2 Increasing complexity

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SLIDE 1

1

Giorgio Buttazzo

g.buttazzo@sssup.it

Scuola Superiore Sant’Anna

2

Context

Embedded systems are becoming more complex every day:

  • more functions
  • higher performance
  • higher efficiency
  • new hardware platforms

Increasing complexity

1990 2000 2010

100 200

# functions in a cell phone 1980 year 2020

300 400 500

Hardware Performance

1990 2000 2010 1980

year

2020

104 106 108 1010 1012

1970

Instructions per second

Intel 8080 M 68000 Intel 286 Intel 386 Intel 486 Intel Pentium Pro DEC Alpha AMD Athlon Xbox 360 (3 cores) Intel i7 (6 cores) AMD Phenom (6 cores)

Software Complexity

year 104 105 106 107 108 Lines of code

1990 2000 2010 1980 2020 1970

MS-DOS 1.0 Windows 3.1 Windows 2000 Windows XP Windows 7 Windows Vista Unix Windows NT 4.0 Linux 3.6 Linux 2.6.0 Linux 2.4.2 Linux 2.6.29 Windows 98 MS-DOS 3.1 Linux 1.1.0 Linux 2.0 Windows 8

And the Result is …

year 30 60 90 120 Boot time (seconds)

1990 2000 2010 1980 2020 1970

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2

It increases with upgrades

files upgraded 2 4 6 8 Boot time (minutes) 1 3 5 7

200K 400K 600K 800K 1M

Windows 7 Windows 8

ECU growth in a car

1990 2000 2010 1980 year 2020 # ECUs

20 40 60 80 100 every function is encoded in a different ECU ECU = Electronic Control Unit

Advantages of separation

Separating functions in dedicated ECUs allows:

  • easier development
  • easier testing
  • easier certification
  • easier maintenance

Problems of separation

With the increasing number of ECUs, there are problems of space, weight, energy.

How to add more functions?

1990 2000 2010 1980 year 2020

30 60 90 120 150 ECUs Functions

no more space current situation: 70 ECUs

Functions group more functions in the same ECU ECUs

That's nice, but

  • How can we test and certify a function in the

presence of other applications?

  • How can we guarantee behavior and performance

to get certification?

A B

ECU1 ECU2

A B

New platform

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SLIDE 3

3

Additional problems

A B

multicore platform single core platform single core platform

  • How do

we partition the applications on the available cores?

  • How does the Worst-Case Execution Time (WCET)

scale on multicore architecture?

A A B A B

14

The problem

When multiple applications run

  • n

the same platform, they interfere with each other due to the use of shared resources. Interference: phenomenon for which the execution

  • f a task affects the one of other tasks.

In the following, we will

  • identify the causes of interference
  • present possible solutions

15

Interference mechanisms

  • Time: concurrent access to shared resources, as

processing units and communication channels.

  • Space: due to sharing the same memory space

(Cache, DRAM, Hard Disk).

  • Energy: sharing the energy source (battery).
  • Temperature: eating up each other.

Tasks may interfere for different reasons:

16

Why do we care?

Because interference has different negative effects:

  • It decreases efficiency and schedulability
  • It reduces predictability
  • It jeopardizes safety
  • It complicates the analysis

17

A simple example

3 4 1 2 Application A CPU 1: speed = 1 Application B

P1 P2 P3 P4

CPU 2: speed = 1 4 3 2 1 Applications A + B Platform: speed = 2

  • Priorities must be assigned
  • Task interference can

jeopardize predictability

P1 P3 P2 P4

18

Priority explosion!

There are 6 priority assignments that satisfy both priority orders: 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 4 2 3 1 2 4 3 1 2 A

P1 P2

3 4 B

P3 P4

How many priority assignments satisfy both priority orders?

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4

19

 How do computation times scale in the new platform?  Which priority order do we choose?  Do they all lead to a feasible schedule?  Are they different in terms of performance?  How can we reduce the reciprocal interference?

Non trivial questions

20 4 8 5 12 10

1 (2,4) 2 (4,8) 3 (2,5) 4 (6,12)

RM schedule (S = 1) RM schedule (S = 1)

A B

4

Let’s go into details

1 2

A

P1 P2 Ci Ti 2 4 4 8 3 4

B

P3 P4 Ci Ti 2 5 6 12

21

Now let’s groups them

How computation times scale in the new platform?

3 4

B

Ci Ti 2 5 6 12

speed = 1

1 2

A

Ci Ti 2 4 4 8

speed = 1

Ci’ = s Ci

Assume for simplicity 1 2

A+B

P1 P2 Ci Ti 4 2 8 3 4 P3 P4 1 5 3 12 1

speed = 2

22

Now let’s groups them

1 2

A+B

P1 P2 Ci Ti 1 4 2 8 3 4 P3 P4 1 5 3 12 1 2 3 4 1 2 3 4 1 2 4 1 3 4 1 2 3 4 1 2 3 4 1 2 3 4

4 8 5 12 4 5 8 12 4 5 12 8 5 4 8 12 5 4 12 8 5 12 4 8

If the new platform has a fixed priority scheduler, what is the best priority order?

RM ordering (optimal)

23 4 8 5 12 10

1 (2,4) 2 (4,8) 3 (2,5) 4 (6,12)

RM schedule (S = 1) RM schedule (S = 1)

A B

1 (1,4) 3 (1,5) 2 (2,8) 4 (3,12)

RM schedule (S = 2)  assuming

A+B

4 8 5 10 12 15 8 16 12

deadline miss

16

A B

All together are not feasible!

C’i = s Ci

24 4 8 5 12 10

1 (2,4) 2 (4,8) 3 (2,5) 4 (6,12)

RM schedule (S = 1) RM schedule (S = 1)

A B

4 8 5 10 8 12 4

Example on 2 cores

Core 1 (S = 1) Core 2 (S = 1)

Rate Monotonic – First Fit or Best Fit

2 4 1 3

miss U = 0.9 U = 1 U = 1 U = 0.9

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5

Course outline - 1

  • 1. Motivation and examples
  • 2. Brief summary of uniprocessor analysis
  • 3. Interference analysis and techniques to reduce it
  • Temporal isolation
  • Resource reservations servers
  • Hierarchical component-based systems
  • Schedulability analysis of single components
  • Resource sharing protocols for hierarchical systems
  • 4. Energy-aware scheduling

Course outline - 2

  • 5. Multiprocessor scheduling
  • Architecture issues and modeling
  • Performance analysis
  • Scheduling paradigms
  • Task allocation and feasibility bounds
  • 6. Processor abstraction and interface
  • Efficient algorithms for the interface design.
  • Multiprocessor abstractions.
  • Applications models.
  • Application partitioning and resource allocation

Course outline - 3

  • 7. Standards for component-based development
  • ARINC: a standard for avionic systems.
  • AUTOSAR a standard for automotive systems
  • 8. Component-oriented programming and models
  • introduction to C++ patterns
  • UML models of components
  • code generation using patterns under Eclipse-EMF
  • 9. Hypervisors
  • The Xen project
  • Guaranteeing

real-time constraints

  • n

hypervisor- based systems