Contents Double Data Rate Interfaces DDR SDRAM Architecture and - - PowerPoint PPT Presentation

2002-12-13

DESIGN AND IMPLEMENTAION OF A DDR SDRAM CONTROLLER

FOR SYSTEM ON CHIP

Magnus Själander

MO/EAB/RTN/D Magnus Själander

2002-12-13 2

Contents

• Double Data Rate Interfaces
• DDR SDRAM Architecture and Functionality
• DDR Memory Controller
• Data Resynchronization
• Floorplan and Place & Route
• Future Work
• Conclusion

MO/EAB/RTN/D Magnus Själander

2002-12-13 3

Double Data Rate Interfaces

Advantages

• Time of Flight
• Clock Skew
• Pin Count
• Bandwidth

Disadvantage

• Synchronization

Clk Data SDR

D0 D1 D2 D3 D4 D5 D6 D7

DDR Clk Data

D0 D1 D2 D3 D4 D5 D6 D7

Data Strobe

Don't care

New

• Data Transmissions on rising and falling edge
• Data Strobe

MO/EAB/RTN/D Magnus Själander

2002-12-13 4

SDRAM Architecture

• Four Banks
• Row and Column Select Lines
• 1T Memory Cells
• Sense Amplifiers
• Global Data Path

Row Decoder Row Decoder Column Decoder and Global Data lines Row Decoder Row Decoder

Central I/O

Row Decoder Row Decoder Row Decoder Row Decoder BL WL BL* Cs CBL BL BL* M

1

VDD SE

*

SE Sense Amplifiers Sense Amplifiers Column Decoder and Global Data lines Sense Amplifiers Sense Amplifiers Column Decoder and Global Data lines Sense Amplifiers Sense Amplifiers Column Decoder and Global Data lines Sense Amplifiers Sense Amplifiers

MO/EAB/RTN/D Magnus Själander

2002-12-13 5

DDR SDRAM Architecture

• 2n-prefetch
• Delay Lock Loop

Address Register Row Decoder Column Buffer Column Decoder Programming Register Latency and Burst Length DLL Strobe Gen. Refresh Counter Row Buffer Bank Select Bank 1 Bank 2 Bank 3 Bank 4 Sense AMP 2n-prefetch Output Buffer I/O Control Input Buffer Data Input Register Serial to Parallel

64 64 32

Timing Register

ADDR CK, CK CK, CK CK, CK CK, CK DQ DQS CKE CS RAS CAS WE DM WEi DMi WEi DMi

MO/EAB/RTN/D Magnus Själander

2002-12-13 6

DDR SDRAM Improvements

• Long Delay in Column

Decode and Data Lines

• Added a Delay Lock Loop to

Increase Clock Frequency

Clk

D0

Data

Read started Data available 7 ns D1

Clk Data

D0 D1 Read started Data available 7 ns

Delayed Clk

Delay 7 ns Clock period 5 ns Clock period

DDR SDRAM SDR SDRAM

MO/EAB/RTN/D Magnus Själander

2002-12-13 7

DDR SDRAM Commands

Same Commands as for Standard SDRAM

• READ
• WRITE
• ACTIVATE
• PRECHARGE
• REFRESH
• MRS (Mode Register Set)

Added

• EMRS (Extended MRS)

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2002-12-13 8

DDR SDRAM Memory Controller

AHB Core Memory Controller DQeven DQodd AHB Buss DDR SDRAM Command Write Data Read Data Command Write Data Command Read Data Read Data DDR SDRAM Memory Controller APB APB Buss Command Data Initialize Address Address Address Data DQ Data Mask DQS Data Strobe

MO/EAB/RTN/D Magnus Själander

2002-12-13 9

Core Memory Controller

Current Address Next Address Open Banks Read Write Command Command Timing Address Address Increment Activate/Precharge Command Read/Write Command Command Address Row Open Command Address Boundary Refresh Refresh Address Address Initialize Initialize Initialization Command Address Enable DQS

MO/EAB/RTN/D Magnus Själander

2002-12-13 10

AHB Interface

Core Memory Controller AHB Buss DDR SDRAM Command Write Data Read Data Write Data Command Read Data Odd AHB Interface Address Address x2 Data Buffer AHB Core Read Data Even Data Addr Data Data Addr Data Command Address DQ even DQ

• dd

Sample Present Increment Counter Data Mask DQ Data Strobe DQS

MO/EAB/RTN/D Magnus Själander

2002-12-13 11

Arbiter

AHB I Core Memory Controller DQeven DQodd AHB Buss 0 DDR SDRAM Command Write Data Read Data Write Data Command Read Data Read Data DDR SDRAM Memory Controller Address Address DQ Data Mask DQS Data Strobe AHB II Command Write Data Read Data Address AHB Buss 1

Arbiter

Command Address Command Address Command Address Write Data Data Mask Write Data Data Strobe Data Strobe

MO/EAB/RTN/D Magnus Själander

2002-12-13 12

Capturing the Data

• Phase Shift the Data Strobe
• Resynchronize the Data

Clk Command

READ NOP NOP

Address

Col n

Data Strobe Data

Don't care

MO/EAB/RTN/D Magnus Själander

2002-12-13 13

Phase Shift the Data Strobe

• Delay Lock Loop
• Inverter Delay
• PCB Line Delay
• Programmable Delay Line with Temperature Sensing

Programmable Delay Line Programmable Look Up Table

Data Strobe Delayed 90o Data Strobe

Temperature Sensor

Digital Delay Line Phase Detector and Control Logic

Data Strobe Data Strobe Delayed 90o

MO/EAB/RTN/D Magnus Själander

2002-12-13 14

Synchronization of the Data

One Flip-Flop for each Flank to Sample

D Q D Q

Data Strobe Data Data Odd Data Even

Data Strobe Data Data Even Data Odd

1 2 3 4 5 6 7 2 4 6 1 3 5 7

Do not care

MO/EAB/RTN/D Magnus Själander

2002-12-13 15

Synchronization of the Data Continued

Reference Clk Clk x2 Data Even Data Strobe

Rising Edge of Data Strobe Data Stable

Reference Clock Low

Reference Clk Clk x2 Data Even Data Strobe

Not stable Rising Edge of Data Strobe Data Stable

Reference Clock High

MO/EAB/RTN/D Magnus Själander

2002-12-13 16

Synchronization of the Data Continued

Simplified Phase Detector

Clk I Clk II Q I Q II Phase

Undefined

D QI D QII

Clk II Clk I High High

& S Q R

Phase Time Line Time Line Time Line

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2002-12-13 17

Floorplan

Data Buffer (AHB II) Data Buffer (AHB I) 630 µm 50 µm 700 µm 15 µm 35 µm 155 µm 50 µm 185 µm 50 µm 155 µm 50 µm 700 µm AHB Interface region 20 µm

DDR Memory Controller DDR Control Signals Address and Data Buss AHB I Read, Write and Address Buss AHB II Read, Write and Address Buss Clock Signals APB Signals AHB I Control Signals AHB II Control Signals

MO/EAB/RTN/D Magnus Själander

2002-12-13 18

Place & Route

AHB II ABH I Data Buffer I Data Buffer II AHB Core AHB x2 APB Refresh Initialization Current Address RW command Command Timing Open Banks Top Arbiter Next Address Data Out

MO/EAB/RTN/D Magnus Själander

2002-12-13 19

Future Work

• Improved Refresh Handling
• Attempt to Reduce Initial Latency for Bursts
• Improved Buffer Handling

MO/EAB/RTN/D Magnus Själander

2002-12-13 20

Conclusion

• Working Implementation
• Smaller Changes to Improve Performance
• Highlights Difficulties and Solutions

2002-12-13

Questions ?