Communication by Qawi Harvard Thesis Defense October 8 th , 2009 - - PowerPoint PPT Presentation

Wide I/O DRAM Architecture Utilizing Proximity Communication

by Qawi Harvard Thesis Defense – October 8th, 2009

Introduction

Bandwidth and power consumption of dynamic random access memory stifles computer performance scaling  Background  Status of Proximity Communication  DRAM Market Analysis  4 Gb DRAM Architecture  Wide I/O DRAM Architecture Utilizing Proximity Communication

2

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Background

 Memory Gap

 Main memory does not scale with processor performance

 Power

 Current consumption is rising  Bandwidth increases power  Voltage scaling masks the issue

 Density

 Memory channel loading  Limits bandwidth

 Proximity Communication

 Proposed by Ivan Sutherland – US Patent #6,500,696  Promises to reduce power and increase bandwidth

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Qawi Harvard – Oct. 8th,2009 Thesis Defense

Proximity Communication

 Capacitive Coupled Proximity Communication

 Top metal forms the parallel plates  Chip-to-chip communication through coupling capacitor

4

Chip 1 Chip 2 Transmit Transmit Receive Receive Chip 1 Chip 2

Ref:[1] Qawi Harvard – Oct. 8th,2009 Thesis Defense

Proximity Communication

 Benefits

 Increased I/O density  Avoids on/off chip wires  Eases chip replacement at the system level  Enhances system level testability  Enables smaller chip sizes  Removes the need for ESD protection

 Challenges

 Mechanical misalignment  Applying power to the chips  Thermal solution

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Ref:[1-5] Qawi Harvard – Oct. 8th,2009 Thesis Defense

Proximity Communication

 Parallel Plate Capacitance  10 pF/mm2

 Chip-to-chip separation  d = 1 µm

 One channel

 50 fF  200 signals/mm2

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d A C  

m aF 

 9 . 8

0 

4000 1000 100 10 2003 2004 2005 2006 2007 2008 2009 2010

Proximity Communication Area Ball Bonding

I/O Density per mm2

[1]

Ref:[1] Qawi Harvard – Oct. 8th,2009 Thesis Defense

Proximity Communication

 Mechanical Misalignment

 Six axis  Multiple sources

7

Separation Tilt Translation Rotation z x y θz θx θy

Ref:[5] Qawi Harvard – Oct. 8th,2009 Thesis Defense

Proximity Communication

 Electronic Sensors

 Chip-to-chip separation sensors (0.2 µm resolution)  Vernier scale incorporated on chip (1.0 µm resolution)

 Electrical Re-Alignment

 Receive array  Micro-transmit array  Electronic steering circuit

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Normalized Received Signal

1.0

20 40 60 80 100 120

0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1

Misalignment (µm) Inactive Transmit Pad Active Transmit Pad Receiver Pad 1 1 1 1 1 1 1 1 1 ?? 1 1 Transmit Chip Receive Chip

Ref:[1-5] Qawi Harvard – Oct. 8th,2009 Thesis Defense

DRAM Market Analysis

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 Revisit the Memory Gap

 “Performance” becomes a relative term  Dichotomy in scaling

 Why Density?  Why Not Latency?

1 10 100 1000 10000 100000 1980 1985 1990 1995 2000 2005 2010 Relative Performance (%) 1 10 100 1000 10000 100000 1980 1985 1990 1995 2000 2005 2010 Relative Performance (%)

Processor IPS DRAM Latency Processor IPS DRAM Density

Ref:[6] Qawi Harvard – Oct. 8th,2009 Thesis Defense

DRAM Market Analysis

 Moore’s Law

 41% increase in transistor count per year

 Selling Price

 36% historic decline per year

 Putting it into Perspective

 1 Gb 2009 → $2.00  2 Gb 2011 → $1.64

 Density or Bust!!

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2001 1997 1974 1976 1977 1988 1986 1979 1980 1978 1981 1982 1983 1984 1985 1987 1999 2003 2004 2005 2002 2000 1998 1996 1994 1995 1992 1993 1991 1990 1989 1975

0.01 0.10 1.00 10.00 100.00 1,000.00 10,000.00 100,000.00 Price per Bit (Milicents)

1 1 0 0 1 0 0 1 0 , 0 0 0 1 , 0 0 0 , 0 0 0 1 0 0 , 0 0 0 , 0 0 0 C u m u l a t i v e B i t V o l u m e (1 0

1 2 1 2 )

Historically the price per bit has declined by 9% every quarter (1974 – 2008). Ref:[7-8] Qawi Harvard – Oct. 8th,2009 Thesis Defense

DRAM Market Analysis

 Cost

 Low cost manufacturing process

• 3 metal layers
• Increased usage of each level
• Small chip size
• Limits I/O count

 Moore’s Law

 41% scaling per year

• Wordline cross sectional area
• Tight metal pitch
• Contact resistance

 Physics of Scaling

 Latency must increase

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Simple RAS/CAS

PM

Fast CAS Access

FPM

Latched Output

EDO

Synchronous w/Clock Multi-Bank Programmable Burst & Latency LVTTL Interface

SDR

Data Clocked on Both Clock Edges Data Strobe SSTL 2.5 Interface

DDR

ODT OCD Posted CAS SSTL 1.8 Interface

DDR2

Standard Low Voltage Option Dynamic ODT Drive/ODT Calibration Write Leveling

DDR3

Faster Lower Power

DDR4

Generations Features

Ref:[7-8,13] Qawi Harvard – Oct. 8th,2009 Thesis Defense

DRAM Market Analysis

 Home PC

 Plugged into a wall

 Mobile

 Battery life

 Server

 Power consumption  Cooling

 Trending Up

 Poor Efficiency  Bandwidth Driven

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Memory Mezzanine Tray (Sun SPARC Enterprise T5240 Server Only)

UltraSPARC UltraSPARC

100 200 300 400 500 600 700 266 333 400 533 666 800 1066 1333 1600 2133 2666 3200

Current Consumption (mA)

Data Rate (MHz)

♦ DDR ■ DDR2 ▲ DDR3

• DDR4

Projections Ref:[14-17] Qawi Harvard – Oct. 8th,2009 Thesis Defense

DRAM Market Analysis

 Interface versus Core

 Interface bares the burden  Core cycles

 DRAM Pre-fetch

 Doubles at each generation

 Density limited by bandwidth

 SSTL loading in memory channel  Increase chip count per module

13

67 67 100 100 267 333 400 533 667 667 800 1066 1333 1600 1600 2133 2666 2666 133 167200 133 167 167 200 133 167 200 200 133 167 167 500 1000 1500 2000 2500 3000 3500 4000

Frequency (MHz)

■ Interface

• Core

DDR (2n) DDR2 (4n) DDR3 (8n) DDR4 (16n) SDR (1n)

400

DIMMS or Devices per Channel

800 1066 1333 1600

Data Rate (MHz)

Ref:[14-17] Qawi Harvard – Oct. 8th,2009 Thesis Defense

4 Gb DRAM Architecture

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SPINE COLUMN ROW  Possible Architecture

 Compared to ITRS

 2012 Production Release  74 mm2  56 % Array Efficiency  40 nm

Ref:[10,12,20-24] Qawi Harvard – Oct. 8th,2009 Thesis Defense

4 Gb DRAM Architecture

15

Memory Capacitor Bitline Wordline 6 F 2 F UNITCELL Isolation Gate

 6F2 Memory Cell  Feature Size = 40 nm  Cell Area = 0.0096 µm2  3F Pitch per Wordline  2F Pitch per Bitline  256 kb Array Macro

 Core Array  512 bitlines ≈ 43.6 µm  512 wordlines ≈ 65.4 µm

 Periphery Circuitry

 4 µm space allocated

UNITCELL UNITCELL UNITCELL

Ref:[24] Qawi Harvard – Oct. 8th,2009 Thesis Defense

4 Gb DRAM Architecture

16

Ref:[25] Qawi Harvard – Oct. 8th,2009 Thesis Defense

4 Gb DRAM Architecture

17

1.9 mm

COLUMN

ROW 256M Array

1.6 mm 2.5 mm 2.3 mm

256M Array

COLUMN

256M Array 256M Array ROW

4.9 mm 3.5 mm CORNER GLOBAL COLUMN

 256 Mb Array

 32 x 32 256 kb macros

 1 Gb Array

 Multiple implementations

 

mm m m 532 . 1 4 6 . 43 32     

Qawi Harvard – Oct. 8th,2009 Thesis Defense

4 Gb DRAM Architecture

18

7.0 mm 10.2 mm

Chip Size = 71.4 mm2 Array Efficiency = 57.7%

SPINE

256M Array Row 256M Array

0.4 mm

Column

256M Array 256M Array

Column

256M Array 256M Array

Column

256M Array 256M Array

Column

256M Array 256M Array

Column

256M Array 256M Array

Column

256M Array 256M Array

Column

256M Array 256M Array

Column

Row Row Row Row Row Row Row

 ITRS

 74 mm2  56% Array Efficiency

 Wide I/O Architecture

 Moving the pads  Centralized Row  Centralized Column

Ref:[29] Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O Chip Architecture

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6.7 mm 10.0 mm

Chip Size = 67.0 mm2 Array Efficiency = 61.5%

4.6 mm

256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array 256M Array RO W RO W Row RO W RO W Row RO W RO W Row RO W

 64 Bytes per Chip  6.2% Chip Size Reduction  6.6% Increase in Array Efficiency  Challenges

 Routing from the edge  Array I/O route increase

• 2.3 mm → 4.6 mm

 Additional row decode

 Create Eight Internal Banks

Row

Proximity Interface

Qawi Harvard – Oct. 8th,2009 Thesis Defense

4 Gb DRAM Architecture

20

 1 mm Allocation for Proximity Channel  Buffers at the Center

 Increase global I/O metal usage

 Array I/O Routing Reduced to 2.3 mm  Architecture NOT Efficient for Proximity Communication

 6.7 mm versus 10.4 mm  Buffers required  Large metal usage

6.7 mm 10.4 mm

Chip Size = 69.68 mm2 Array Efficiency = 59.2%

Proximity Interface

2.3 mm

512M Bank ROW 512M Bank 512M Bank ROW 512M Bank 512M Bank ROW 512M Bank 512M Bank ROW 512M Bank

3.2 mm 7.0 mm Qawi Harvard – Oct. 8th,2009 Thesis Defense

4 Gb DRAM Architecture

21

1-8k Page ≈ 0.8 mm 64k Rows ≈ 8.9 mm

512M Bank

A

2-8k Pages ≈ 1.5 mm 32k Rows ≈ 4.5 mm

512M Bank

B

16k Rows ≈ 2.3 mm

512M Bank

4-8k Pages ≈ 3.0 mm

C

8k Rows ≈ 1.1 mm 8-8k Pages ≈ 6.1 mm

512M Bank

D

 Multiple Bank Architectures  Page Size

 Standard size = 8k  Energy efficiency

 Global Row Routing

 ~20 ns latency

 Global Column Routing

 ~5 ns latency

 D – Architecture

 Page decode

Ref:[13,16,27,30,] Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O Chip Architecture

22

12.3 mm

Proximity Interface

ROW 512M Bank

6.0 mm

512M Bank 512M Bank 512M Bank 512M Bank 512M Bank 512M Bank 512M Bank ROW COLUMN COLUMN

5.6 mm 2.4 mm

 Chip Size = 68.88 mm2, Array Efficiency = 59.9%

 Centralized row & column  Buffers not required  12.3 mm for proximity communication  Enables two levels of metal

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O DRAM Architecture

 Split Bank Architecture

 64 bytes = 512 signals  6 mm / 256 ≈ 43 µm per signal  0.4 µm pitch < 1 % metal usage

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Proximity Interface

ROW

Half-Bank<0>

COLUMN COLUMN

Half-Bank<2> Half-Bank<3> Half-Bank<4> Half-Bank<5> Half-Bank<6> Half-Bank<7> Half-Bank<4> Half-Bank<5> Half-Bank<6> Half-Bank<7> Half-Bank<0> Half-Bank<2> Half-Bank<3>

RAS & Address Local Wordline Global Wordline

ROW ROW ROW ROW ROW

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O DRAM Architecture

 Split Page Architecture

 8k page keeps current relative  Page decode required  32 differential signals per macro

 Local I/O Routing

 Space limited  Increase space?  Increase page size?

24

800 µm DQ<64:61> Region DQ<60:57> Region DQ<3:0> Region

Half-Bank

BLSA BLSA 32 LIO 256 BL 32 LIO 256 BL

Ref:[12,20-24,26,28] Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O DRAM Architecture

 New Column Routing

 Global I/O operates at higher frequency  Protocol allows for insertion of data

25

BUSY Half-Bank<5> Half-Bank<6> Half-Bank<0> Half-Bank<1> Half-Bank<2> Half-Bank<3> FREE FREE BUSY FREE FREE FREE FREE Half-Bank<7> Half-Bank<6> Half-Bank<5> Half-Bank<4> Half-Bank<3> Half-Bank<2> Half-Bank<1> Half-Bank<0> Proximity Interface Wordline Fires Next Wordline Fires Data Latched & Inserted on Global I/O Bus Data Latched & Inserted on First Available Slot of the Global I/O Bus Global I/O Bus

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O DRAM Architecture

 Slice Architecture

 Ease of design

• Uniformity, speed, verification

26

Proximity Interface

Half-Bank<0>

ROW

COLUMN

ROW ROW ROW ROW ROW ROW ROW

Half-Bank<1> Half-Bank<2> Half-Bank<3> Half-Bank<4> Half-Bank<5> Half-Bank<6> Half-Bank<0> DATA SLICE

50 µm Serves 4 DQ

DATA SLICE CONTROL SLICE Redundancy

Control Latches (Pre)Decode (De)Serializer RD/WR Drivers Buffers

Proximity x4 Interface

DQ<3:0> GIO<7:0> ADDRESS CONTROL Command Address

Power Power

Fuses

Proximity x24 Interface

CONTROL CONTROL ADDRESS CLOCK ADDRESS

Control Logic Address Latch Buffers Refresh Clock Rx Command Decode ADD/CMD Rx Buffers to Left Buffers to Right

Metal Routing Data SLICE Control SLICE Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O DRAM Architecture

 64 Bytes per Chip

 Significant bandwidth increase

 Power Consumption

 Standard 8k page size  Split bank, split page

 Cost Performance

 Two metals enabled for 4 Gb  Smaller chip size, higher array efficiency

27

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O DRAM Architecture

 Power Consumption

28

100 90 80 70 60 50 40 30 20 10

PxCDRAM x64 PxCDRAM x32 PxCDRAM x16 DDR3

Relative Energy [%]

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Wide I/O DRAM Architecture

 Bandwidth

29

200 175 150 125 100 75 50 25

2009

Module Bandwidth [GB/s]

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019

225

DDR5 DDR4 DDR3 PxCDRAM x16 PxCDRAM x32 PxCDRAM x64

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Future Work

 Applying Proximity Communication to New Memory Technologies

 “High” density  Chalcogenide  Slice architecture  Circuit design techniques

 Local I/O Routing

 New column global I/O structure  Through bitline routing  Novel local I/O latch

30

Qawi Harvard – Oct. 8th,2009 Thesis Defense

Acknowledgments

 Dr. Jake Baker  Dr. Kris Campbell  Dr. Robert Drost  Dr. Sin Ming Loo  Dr. Thad Welch  Ms. Donna Welch  Family support

Questions?

31

Qawi Harvard – Oct. 8th,2009 Thesis Defense

References

32

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Conference, vol. 39, issue 9, pp. 469-472, September 2003. [2] D. Salzman, T. Knight, “Capacitively Coupled Multichip Modules,” Multichip Module Conference Proceedings, pp. 487- 494, April 1994. [3] R. Drost, R. Ho, R. Hopkins, I. Sutherland, “Electronic Alignment for Proximity Communication,” IEEE International Solid State Circuits Conference, vol. 1, pp. 144-145, February 2004. [4]

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Qawi Harvard – Oct. 8th,2009 Thesis Defense

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Qawi Harvard – Oct. 8th,2009 Thesis Defense

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[33] Hewlett-Packard, “Memory technology evolution: an overview of system memory technologies, technology brief, 8th edition,”: http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf, April 2009. [34]

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Qawi Harvard – Oct. 8th,2009 Thesis Defense