Clocks for 4.5G Radio Access Networks S E P T E M B E R 2 0 1 7 - - PowerPoint PPT Presentation

Clocks for 4.5G Radio Access Networks

S E P T E M B E R 2 0 1 7

Complete Timing Portfolio

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• Leader in high performance clocks and oscillators
• Frequency flexibility + ultra-low jitter
• Best-in-class integration  single IC clock trees
• Highly programmable with quick-turn samples

XO/VCXO Clock Buffers Clock Generators Jitter Attenuating Clocks Synchronization Wireless Clocks

• Road to 5G Starts Now

Silicon Labs Confidential

Raise awareness of new products Si534x, Si538x, Si54x/Si56x, Si52200, Si5332 Small Cells Expand coverage and capacity in dense urban metro environments

5G

Distributed Antenna Systems Boost coverage inside buildings, stadiums, subways, malls, airports Backhaul Equipment High bandwidth fiber or microwave

Core Router

Core / Metro

Packet-Optical Transport Data Center Interconnect

10G  100G / 400G

Trends

Data Center

40G  100G Mobile Edge Computing

Servers Switches Storage

Wireless

LTE-Advanced, 4.5G, 5G Massive MIMO, IEEE 1588

RRH BBU Small Cells MDAS Fronthaul / Backhaul

Applications

Delivering optimized timing solutions combining highest performance and integration

Timing Focus Markets

History of Innovation

Industry’s first jitter attenuating CLK IC Industry’s first quad frequency XO/VCXOs Industry’s first any-rate jitter attenuating CLK Industry’s first multi-format low jitter buffer 2002 2005 2007 2008 2017 2012 Industry’s first any-rate CLK generator Industry’s first 100 fs any-rate jitter attenuating CLK 2016 Industry’s first Coherent optical CLK Available Now! Industry’s first 2014 LTE + Ethernet CLKs Industry’s first <100 fs any-rate XOs

DSPLL Simplifies Low Jitter Clock Generation

Two-Stage Cascaded PLL:

• 1st stage: jitter cleaning, 2nd stage: clock generation
• Requires discrete VCXO, loop filters, LDOs
• Susceptible to board-level noise coupling
• High power, BiCMOS technology

>100 U.S. and international patents issued or filed for Silicon Labs timing technology

Phase Detector & ADC Digital Loop Filter DCO

fIN

fOUT

DSPLL Outer Loop

Frac-N Divider Phase Detector Loop Filter VCO Frac-N Divider

XO DCO OUT

DSPLL Inner Loop

Low Phase Noise Clock Generation Jitter Cleaning

Two-Stage Nested DSPLL:

• Provides jitter cleaning and clock generation
• No external VCXO, loop filters; eliminates VCXO LDO
• Highly immune to board-level noise
• >50% lower power, 55 nm CMOS technology

MultiSynth Technology = Any Frequency Flexibility

Conventional approach

• Configuration-dependent jitter
• No phase error cancellation
• Highly variable jitter generation
• Non-zero ppm frequency synthesis error

Silicon Labs approach

• Dynamic phase error cancellation minimizes jitter
• Consistent, low jitter operation
• Zero ppm frequency synthesis error
• Any frequency with <100 fs rms jitter

fVCO fOUT Frac-N Divider

Divider Select

Fractional Divider

fVCO fDIV fOUT

Phase Adjust Frac-N Divider

Phase Error Cancellation

e

Divider Select (DIV1, DIV2)

MultiSynth

• Single IC  highest integration
• Optimized LTE + Ethernet clocking
• 94 mm2 PCB area
• 1.1 W power consumption

Simplifying Timing For Small Cells, DAS and Backhaul

8 Silicon Labs Confidential

VCXO Jitter Cleaning Clock Clock Generator

Loop Filter 4G/LTE JESD204B Clocking

• Gen. Purpose Clocking

SerDes DACs DACs DACs ADCs DFE / FPGA / Baseband Processor SerDes DACs DACs DACs ADCs Fiber Microwave Mm-wave DFE / FPGA / Baseband Processor

Si5386/81

Wireless PLL Ethernet PLL

Traditional Approach

Fiber Microwave Mm-wave

• Requires 2 clock IC’s and VCXO
• Not optimized for size, power, cost
• 339 mm2 PCB area
• 2.4 W power consumption

Low Phase Noise – DSPLL Replaces 30.72 MHz VCXO-Based PLLs

9 Silicon Labs Confidential

Si538x with no VCXO at 122.88MHz LMK04828 with 30.72 MHz VCXO at 122.88MHz

Better performance without the cost and PCB area of a VCXO

The Si538x Integration Advantage is Clear

10 Silicon Labs Confidential

BOM Components Cascaded PLL Si5381/82/86 DSPLL DUT area 81 81 VCXO area 151 8 Loop filter area 9 Power supply filtering 31 4 Fractional Clock IC area 49 Other PCB area 18 2 Total PCB footprint 339 mm2 95 mm2 Power Consumption 2.4 W 1.0 – 1.5 W

70% smaller and 55% lower power than competing devices

Si5386 1-DSPLL Wireless Clock

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IN_SEL IN0 IN3/FB_IN ÷INT ÷INT DSPLL RST PDN OE SYNC SDA/SDIO A1/SDO SCLK A0/CS I2C_SEL SPI/ I

2C

LOL Status Monitors INTR OSC Integrated XO Circuit OUT0 ÷INT OUT1 ÷INT OUT2 ÷INT OUT0A ÷INT NVM Multi Synth Multi Synth Multi Synth OUT4 ÷INT OUT5 ÷INT OUT6 ÷INT OUT3 ÷INT OUT8 ÷INT OUT9 ÷INT OUT9A ÷INT OUT7 ÷INT IN1 ÷INT IN2 ÷INT Multi Synth Multi Synth

Si5386

• 5 independent frequency domains
• RF transceivers
• Data converter clocks
• CPRI, Ethernet, CPU clocks
• No external VCXO, crystal, loop filters
• Hitless switching, holdover
• Optional zero delay mode

Part Number

• No. of Clock

ck Domains Clock Inputs/ Outputs Input Frequency cy Output Frequency cy Phase Jitter (fs RMS) S) PLL Bandwi width Pack ckage Si5386 5 4/12 7.68 MHz to 750 MHz 100 Hz to 2.94912 GHz 80 10 Hz to 4 kHz 64 LGA 9x9 mm

• Small cells
• Pico cells, femto cells
• Low phase noise, spurious & jitter
• Noise floor: -165 dBc/Hz
• Spur: -103 dBc @ 122.88 MHz
• 80 fs RMS jitter
• Configurable swing: 200-3200 mVpp

APPLICATIONS FEATURES

• Fixed wireless
• Distributed Antenna Systems

• Base Band Unit
• DSPLL for 4G/LTE Clocks to ADC/DAC
• DSPLL for SyncE
• DSPLL for FPGA clocking
• Small Cells / Distributed Antenna Systems
• DSPLL for RF transceiver
• MultiSynth channel generates Ethernet frequencies

New Solutions for Wireless

DSPLL B LTE DSPLL A SyncE DSPLL Wireless MultiSynth Ethernet DSPLL C FPGA

CPRI 30.72MHz x N SyncE 8kHz x N XO CPRI 30.72MHz x N

• r

eCPRI 156.25MHz Si5381 Si5386

Si5381/82 Multi-DSPLL Wireless Clock

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• 2 or 4 independent timing paths
• ANY in to ANY out frequency per DSPLL
• No external VCXO, crystal, loop filters
• Hitless switching, holdover
• Optional zero delay mode
• Mobile backhaul
• LTE-Advanced, 4.5G
• DSPLL B optimized for wireless
• Noise floor: -165 dBc/Hz
• Spur: -103 dBc @ 122.88 MHz
• 80 fs RMS jitter
• DSPLL A/C/D for reference & data
• FPGA, CPU, SyncE

APPLICATIONS FEATURES

• Fixed wireless
• Base band units, micro-BTS

Si5381/82

DSPLL C DSPLL A DSPLL D

IN1 IN2 IN3 IN0 OUT6 OUT5 OUT4 OUT0 OUT3 OUT2 OUT1 OUT0A ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT

Si5382

NVM I2C/SPI Control/ Status OSC

Si5381

OUT9A OUT9 OUT8 OUT7 ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT ÷INT

DSPLL B

Integrated XO Circuit

Part Number # PLLs Clock Inputs/ Outputs Input Frequency cy Output Frequency cy Phase Jitter (fs rms) PLL Bandwidth Pack ckage Si5381 4 4/12 8 kHz to 750 MHz 100 Hz to 2.94912 GHz 80 10 Hz to 4 kHz 64 QFN 9x9 mm Si5382 2

Product Comparison Table

Silicon Labs Confidential

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Feature Si5381/Si5382 Si5386

• No. Of Clock

Inputs/Outputs 4/12 (differential) 4/12 (differential)

• No. of DSPLLs

4/2 1

• No. of Frequency

Domains Four independent DSPLLs Five MultiSynths Integrated VCXO and Loop Filter Yes Yes Integrated Reference Yes: no external xtals or

• scillators

Yes: no external xtals or

• scillators

Zero Delay Mode Yes Yes Package 9x9 mm 64-LGA 9X9 mm 64-LGA Power Consumption 1.4W/1.1W 1.0W

Si538x Development Tools

15 Silicon Labs Confidential

Find the right clock and customize it for your application Test on an Evaluation Board Create custom part number Contact Sales or Distributor and place sample order Receive pre-programmed samples in 2 weeks Start Here

• Click here to download ClockBuilder Pro
• Si538x development kits:
• Si5381E-E-EVB, Si5382E-E-EVB, Si5386E-E-EVB

Summary: Si538x Simplify Wireless Clock Trees

16 Silicon Labs Confidential

• Highest level of integration
• Eliminates clocks ICs, VCXO, loop filters, LDOs
• Simplifies PCB layout, power supply filtering

Carrier-grade performance

• Low phase noise
• Excellent spurious performance
• More reliable than VCXO-based PLL

Best-in-class integration

• Simplified PCB layout and design
• Intuitive ClockBuilder Pro software

Simple, easy to use

www.silabs.com/timing