Clocks for 4.5G Radio Access Networks S E P T E M B E R 2 0 1 7 - PowerPoint PPT Presentation

Clocks for 4.5G Radio Access Networks S E P T E M B E R 2 0 1 7

Complete Timing Portfolio  Leader in high performance clocks and oscillators  Frequency flexibility + ultra-low jitter  Best-in-class integration  single IC clock trees  Highly programmable with quick-turn samples XO/VCXO Clock Generators Clock Buffers Synchronization Jitter Attenuating Clocks Wireless Clocks 2

Road to 5G Starts Now Backhaul Equipment High bandwidth fiber or 5G microwave Distributed Antenna Systems Boost coverage inside buildings, stadiums, subways, malls, airports Small Cells Raise awareness of Expand coverage and new products Si534x, capacity in dense urban Si538x, Si54x/Si56x, metro environments Si52200, Si5332 Silicon Labs Confidential 

Timing Focus Markets Core / Metro Data Center Wireless 40G  100G LTE-Advanced, 4.5G, 5G 10G  100G / 400G Trends Mobile Edge Computing Massive MIMO, IEEE 1588 Small Cells MDAS Core Router Servers Applications Packet-Optical Switches RRH BBU Transport Data Center Storage Fronthaul / Backhaul Interconnect Delivering optimized timing solutions combining highest performance and integration

History of Innovation Available Now! Industry’s first LTE + Ethernet Industry’s first Industry’s first Industry’s first CLKs quad frequency any-rate 100 fs any-rate jitter XO/VCXOs CLK generator attenuating CLK Industry’s first Industry’s first Industry’s first Industry’s first Industry’s first jitter attenuating multi-format low any-rate jitter Coherent optical <100 fs any-rate CLK IC jitter buffer attenuating CLK CLK XOs 2002 2005 2007 2008 2012 2016 2017 2014

DSPLL Simplifies Low Jitter Clock Generation Two-Stage Cascaded PLL:  1 st stage: jitter cleaning, 2 nd stage: clock generation  Requires discrete VCXO, loop filters, LDOs  Susceptible to board-level noise coupling  High power, BiCMOS technology >100 U.S. and international patents issued or filed for Silicon Labs timing technology Two-Stage Nested DSPLL: Low Phase XO Phase Loop DCO VCO Detector Filter OUT Noise Clock Generation Frac-N  Provides jitter cleaning and clock generation Divider DSPLL Inner Loop  No external VCXO, loop filters; eliminates VCXO LDO  Highly immune to board-level noise Digital f IN Phase Loop DCO f OUT Detector Jitter Filter & ADC  >50% lower power, 55 nm CMOS technology Cleaning Frac-N Divider DSPLL Outer Loop

MultiSynth Technology = Any Frequency Flexibility Conventional approach Fractional Divider  Configuration-dependent jitter Frac-N  No phase error cancellation Divider f VCO f OUT  Highly variable jitter generation Divider Select  Non-zero ppm frequency synthesis error Silicon Labs approach MultiSynth  Dynamic phase error cancellation minimizes jitter Frac-N Phase Divider Adjust f VCO f DIV f OUT  Consistent, low jitter operation e Phase Error Cancellation  Zero ppm frequency synthesis error Divider Select (DIV1, DIV2)  Any frequency with <100 fs rms jitter

Simplifying Timing For Small Cells, DAS and Backhaul Traditional Approach Gen. Purpose Clocking 4G/LTE JESD204B Clocking Si5386/81 Jitter VCXO Clock Cleaning Wireless PLL Generator Loop Clock Ethernet PLL Filter DACs Fiber DACs Fiber DFE / FPGA / ADCs DFE / FPGA / SerDes ADCs SerDes Microwave Microwave Baseband Baseband DACs Mm-wave Mm-wave DACs Processor Processor DACs DACs  Requires 2 clock IC’s and VCXO  Single IC  highest integration  Not optimized for size, power, cost  Optimized LTE + Ethernet clocking  339 mm 2 PCB area  94 mm 2 PCB area  2.4 W power consumption  1.1 W power consumption 8 Silicon Labs Confidential

Low Phase Noise – DSPLL Replaces 30.72 MHz VCXO-Based PLLs Si538x with no VCXO at 122.88MHz LMK04828 with 30.72 MHz VCXO at 122.88MHz Better performance without the cost and PCB area of a VCXO 9 Silicon Labs Confidential

The Si538x Integration Advantage is Clear Si5381/82/86 BOM Components Cascaded PLL DSPLL DUT area 81 81 VCXO area 151 8 Loop filter area 9 0 Power supply filtering 31 4 Fractional Clock IC area 49 0 Other PCB area 18 2 339 mm 2 95 mm 2 Total PCB footprint Power Consumption 2.4 W 1.0 – 1.5 W 70% smaller and 55% lower power than competing devices 10 Silicon Labs Confidential

Si5386 1-DSPLL Wireless Clock Si5386 Clock Phase Part No. of Clock ck Input Output PLL Inputs/ Jitter Pack ckage Integrated XO Circuit Number Domains Frequency cy Frequency cy Bandwi width Outputs (fs RMS) S) IN_SEL 7.68 MHz 100 Hz to OSC 10 Hz to 64 LGA Si5386 5 4/12 to 2.94912 80 IN0 ÷INT 4 kHz 9x9 mm 750 MHz GHz DSPLL IN1 ÷INT ÷INT OUT0A APPLICATIONS IN2 ÷INT OUT0 ÷INT IN3/FB_IN ÷INT  Small cells  Fixed wireless 0 OUT1 ÷INT Multi  Pico cells, femto cells  Distributed Antenna Systems OUT2 ÷INT Synth OUT3 ÷INT Multi Synth FEATURES OUT4 ÷INT Multi  5 independent frequency domains  Low phase noise, spurious & jitter Synth 0 OUT5 ÷INT Multi  RF transceivers  Noise floor: -165 dBc/Hz I2C_SEL Synth OUT6 ÷INT  Data converter clocks SDA/SDIO  Spur: -103 dBc @ 122.88 MHz SPI/ Multi A1/SDO OUT7 2 C ÷INT I Synth  CPRI, Ethernet, CPU clocks SCLK  80 fs RMS jitter A0/CS OUT8 ÷INT NVM  No external VCXO, crystal, loop filters  Configurable swing: 200-3200 mVpp 0 OUT9 ÷INT LOL Status  Hitless switching, holdover Monitors INTR OUT9A ÷INT  Optional zero delay mode PDN RST SYNC OE 11

New Solutions for Wireless Si5381 Si5386 DSPLL DSPLL B CPRI CPRI Wireless 30.72MHz x N LTE 30.72MHz x N or eCPRI DSPLL A SyncE MultiSynth 156.25MHz 8kHz x N SyncE Ethernet DSPLL C XO FPGA  Base Band Unit  Small Cells / Distributed Antenna Systems  DSPLL for 4G/LTE Clocks to ADC/DAC  DSPLL for RF transceiver  DSPLL for SyncE  MultiSynth channel generates Ethernet frequencies  DSPLL for FPGA clocking

Si5381/82 Multi-DSPLL Wireless Clock Clock Phase Part Input Output PLL Si5381/82 # PLLs Inputs/ Jitter Pack ckage Number Frequency cy Frequency cy Bandwidth Outputs (fs rms) Integrated XO Circuit Si5381 4 8 kHz 100 Hz to 10 Hz to 64 QFN 4/12 to 2.94912 80 OSC 4 kHz 9x9 mm 750 MHz GHz Si5382 2 ÷INT OUT0A ÷INT OUT0 DSPLL APPLICATIONS IN0 ÷INT C ÷INT OUT1  Mobile backhaul  Fixed wireless DSPLL IN1 ÷INT ÷INT D OUT2  LTE-Advanced, 4.5G  Base band units, micro-BTS DSPLL ÷INT OUT3 IN2 ÷INT A FEATURES ÷INT OUT4 DSPLL IN3 ÷INT B ÷INT OUT5  2 or 4 independent timing paths  DSPLL B optimized for wireless Si5381 ÷INT OUT6  Noise floor: -165 dBc/Hz  ANY in to ANY out frequency per DSPLL ÷INT OUT7  Spur: -103 dBc @ 122.88 MHz Si5382  No external VCXO, crystal, loop filters NVM ÷INT  80 fs RMS jitter OUT8 I 2 C/SPI  Hitless switching, holdover ÷INT OUT9  DSPLL A/C/D for reference & data Control/ Status  Optional zero delay mode ÷INT OUT9A  FPGA, CPU, SyncE 13

Silicon Labs Confidential Product Comparison Table Feature Si5381/Si5382 Si5386 No. Of Clock 4/12 (differential) 4/12 (differential) Inputs/Outputs No. of DSPLLs 4/2 1 No. of Frequency Four independent Five MultiSynths Domains DSPLLs Integrated VCXO and Yes Yes Loop Filter Yes: no external xtals or Yes: no external xtals or Integrated Reference oscillators oscillators Zero Delay Mode Yes Yes Package 9x9 mm 64-LGA 9X9 mm 64-LGA Power Consumption 1.4W/1.1W 1.0W 14

Si538x Development Tools Find the right clock and customize it for your application Start Test on an Evaluation Board Here Create custom part number Contact Sales or Distributor and place sample order Receive pre-programmed samples in 2 weeks  Click here to download ClockBuilder Pro  Si538x development kits:  Si5381E-E-EVB, Si5382E-E-EVB, Si5386E-E-EVB 15 Silicon Labs Confidential

Summary: Si538x Simplify Wireless Clock Trees  Highest level of integration Best-in-class integration  Eliminates clocks ICs, VCXO, loop filters, LDOs  Simplifies PCB layout, power supply filtering  Low phase noise Carrier-grade performance  Excellent spurious performance  More reliable than VCXO-based PLL  Simplified PCB layout and design Simple, easy to use  Intuitive ClockBuilder Pro software 16 Silicon Labs Confidential

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