Chapter 4 The Wire Wiring analysis is essential for: Speed Power - - PowerPoint PPT Presentation

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Apr 27, 2023 300 likes •393 views

Digital IC-Design The Wire & decreasing feature sizes Dynamic behavior change in deep submicron A Active elements are less dominant i l l d i Chapter 4 The Wire Wiring analysis is essential for: Speed Power Reliability Parasitics

SLIDE 1

1 Digital IC-Design

Chapter 4 The Wire

The Wire & decreasing feature sizes

Dynamic behavior change in deep submicron A i l l d i Active elements are less dominant Wiring analysis is essential for: Speed Power Reliability

Parasitics

Bonding wire inductance Wire parasitics Pin capacitance

Wire Parasitics

Wire

Parasitic classes Capacitive

Substrate Wire

Resistive Inductive Reduces Performance Increase Power Consumption Affect Reliability

SLIDE 2

2 Resistive (Inductive) Parasitics

VDD R ISwitch

VDD

V

DD

RWire

Supply is Provided from Outside

Package Capacitance (pF) Inductance (nH) Package Capacitance (pF) Inductance (nH) 68 Pin Plastic DIP 4 35 68 Pin Ceramic DIP 7 20 256 Pin Grid Array 5 15 Bond Wire 1 1 Solder Bump 0 5 0 1 Solder Bump 0.5 0.1

Source: Sze

Capacitive and Inductive Coupling

A voltage or a current change may influence

CCoupling V I M t l

change may influence the signal on a parallel wire, especially on:

Long wires Sub micron technologies S l t l l

Mutual Inductance I

Several metal layers

Interconnect

0.08 Connection Probability

Local Wires Global Wires

0.06 0.04

Gl b l Wi d t

0.02 1.0 0.2 0.8 0.6 0.4 Wire Length/Chip Diagonal Length

Global Wires do not scale with the technology

SLIDE 3

3 Metal Layers - Not a 2D problem!!!

Transistors Transistors Tungsten Contacts Tungsten Contacts Long wires affect Long wires affect the performance the performance

Metal Layers Capacitance: Parallel Plate

SiO

Metal/Poly etc.

SiO2 t L H W

WL C t ε =

Substrate

tox ε

−

= ×

15 2

Permitivity 3.5 10 / for SiO

F cm

Capacitance: Fringing

H W H W H W

SLIDE 4

4 Metal Layers Metal Contacts (via)

Note

Fringing C

the Size!

Capacitance Values

Typical 0.35μ process yp μ p

Layer Plate Cap. fF/um2 Fringing Cap. fF/um Poly to Substrate 0,119 0,051 Metal1 to Substrate 0,031 0,043 Metal2 to Substrate 0,012 0,031

Per fringe!

Example: Calculate the Wire Cap.

10x10 mm Chip

0.35μ Technology

15 6

0 031 10− ⋅

6 12 15 6

0.031 10 0.1 1 10 10 3.1 pF 0.043 10 0.1 10 8 6 pF

plate fringe

C C

− − − −

= × ⋅ × = = ⋅ = × × =

Δ L = 15mm

CLK

Total Length 0.1 m 1μm wide

8.6 pF 11.7 pF

tot plate fringe

C C C = = + = 6 Capacitance pF/cm

Impact of Fringing Capacitance

Fringing capacitance

1 Cplate T/H=1 T/H=0.5

dominates for small W/H

In 0.35μ W≈ H≈ T

0.1 0.1 10 1 0.4 W/H 4

plate

T H

SLIDE 5

5 Interwire Capacitance

Metal2

Cross-talk

Poly Metal1

Substrate

Poly

Interwire Capacitance

Typical 0.35μ process

Layer Area Cap. fF/um2 Fringing Cap. fF/um Poly to Metal1 0,054 0,050 Metal1 to Metal2 0,035 0,043 Poly to Metal2 0,015 0,033

Per fringe!

Wire Resistance

Sheet Resistance

R

L L R R ρ = × = ×

R R R R R

R R

W H W

Metal/Poly etc.

H W

R R

R R R R

Sheet Resistance

Typical Values 0.25 μm technology

M i l Sh R i Material Sheet Resistance

Diffusion 50-150 Ω/ Well 1000-15000 Ω/ Polysilicon 150-200 Ω/ Poly with Silicide 4-5 Ω/ Aluminum 0.05-0.10 Ω/

SLIDE 6

6 Example: Calculate the Wire Resistance

10x10 mm Chip

0.25μ Technology

0.01 0.1 1 10 1 k L R R W

−

= × = × = ⋅ = Ω

Δ L = 15mm

CLK

Longest Length = 10mm 1μm wide

Silicide

Silicide to reduce the poly resistance

Polysilicon Silicide SiO2

n+ p- n+

Conductivity: 8-10 times better than Poly

Advanced technologies have silicide on polysilicon

Silicides: WSi2, TiSi2, PtSi2, and TaSi

Optimal wiresizing

Minimum delay wire has an exponential taper Optimal tapering improves delay by about 8% Implemented with boxes

Source: Wayne Wolf

Optimized tree

Source Sink 1 Sink 2

SLIDE 7

7 The Lumped Model

Vout V Rdriver Cwire

Driver

(1 )

t RC

V V

−

Vout Clumped

Model

(1 )

V e V = −

Delay Definitions

VIN

(1 )

t RC

V e V

−

= −

VOUT t 50% tpLH tpHL 90%

90 10

in r

t t t = −

t 50% tf tr 10%

Rise-Fall time

90 10

(1 ) ;

t RC

in r

V e V t t t

−

= − = −

Vout R

0.1 (1 ) 0.9 ln(0.9)

RC in in t RC

V e V e t RC

− −

= − ⇔ = ⇔ = −

ln(0.1) t RC = −

C

90 10

( ln(0.1) ln(0.9)) 2.2

r r

t t t RC t RC = − = − + = =

50 50

ln(0.5) 0.69 t RC t RC = − = =

Distributed RC-Line

Lumped

R R

Lumped Model Distributed

r Δ L C C c Δ L r Δ L r Δ L c Δ L c Δ L

Model

L

c Δ L c Δ L c Δ L

SLIDE 8

8 RC-Models

Lum ped Distributed t p (0 -> 50% ) 0.69RC 0.38RC RC (0 -> 63% ) RC 0.5RC t r (10% -> 90% ) 2.2RC 0.9RC

Lumped model tends to be pessimistic

Driving a Wire

Vout Rs Rw Vout Cw

2.2 0.9 (2.2 0.9 )

r s w w w s w w

t R C R C R R C = + = +

RC-Models

2 C 2 C

C 2 R 2 R 3 R 3 R 3 R 4 C 2 C 2 R 4 C 2 R 6 R 6 R 3 R 3 R 2 C 4 R 2 C 4 R 2 R

π-Models T-Models

6 C 6 C

3 C 3 3 C 3 3 6 3 C 3 C 6 3 C 3 3

The Elmore Delay

1 1 1 2 2 1 2 3 3 1 2 3 4 4

τ R C (R R )C (R R R )C (R R R R )C = + + + + + + + + +

R6 R5 R4 R3 R2 R1 C4 C5 C6 C3 C2

SLIDE 9

9 The Elmore Delay

1 1 1 2 2 1 2 3 3 1 4

τ R C (R R )C (R R R R C )C = + + + + + +

C4 R1 C R4 Vin

C4 is loaded through R1 R4 do not affect the delay at Vout

C1 C3 R2 C2 R3 Vout

Electro Migration

1mA/um I

max DC,

≈

Electro Migration Avoiding Electro Migration

Many contacts for higher currents