Chapter 3 Introduce basic device equations Introduce models for - - PowerPoint PPT Presentation
Digital IC-Design This chapter will Present intuitive understanding of the device operation device operation Chapter 3 Introduce basic device equations Introduce models for manual analysis The Devices Show secondary and deep-sub-micron
Present intuitive understanding of the device operation device operation Introduce basic device equations Introduce models for manual analysis Show secondary and deep-sub-micron effects effects Show future trends
One- dimensional IC- structure
p- n+ p+ SiO2 Metal Semi- conductor n+ p+
Thin
transition = abrupt junction
Diodes appears reverse biased in all MOS-transistors Protects input
Bonding Wire
VDD
They have parasitics that affects the performance (speed, power) Protects input devices against static charges
To Core ”Protected” Pad Surface
(
D T
V D S
I I eφ = ×
Exponential First Order
Model Model Fixed voltage VDon “threshold”
2 5
The diode current ID has an exponential behavior regarding the voltage VD
D
V φ
ID (mA) 1.5 2.5 0.5
Forward biased
T
D S
VD (V)
1
Backward biased
Forward “not allowed”
Affects the maximum speed (how fast the charges can be removed) Aff t th d i ti Affects the dynamic power consumption The diode can be seen as a capacitor Charges are built
Di t Charge density Current + Diode p n
Charges are built up around the pn- junction
Distance +
Strongly non-linear capacitance
F C 0
2 1/ 2 2
F (derived at page 82) m (1 ) F = zero-bias capacitance in (when 0)
j j D j D
C C V C V = − Φ =
Cj0 and Φ0 are physical device parameters
2
p ( ) m = built-in potential
j D
Φ
Determine the junction capacitance for
2
0.5 μm (junction area)
D
A = Cj when VD=0
3 2 3 3
μ (j ) F 2 10 m 0.64 V 2.5 V 2 10 F
D j D j
C V C
− −
= × Φ = = − × Cj when VD Cj when VD=-2.5 Small but billions of them give a high
3 2 1/ 2 1/ 2 12 3 15
2 10 F 0.9 10 2.5 m (1 ) (1 ) 0.64 0.50 10 0.9 10 0.45 10 0.45 fF
j j D Diode D j
C V C A C
− − − −
× = = = × − − − Φ = × = × × × = × = g g total C
Abrupt pn-junctions have a thin transition region Integrated pn-junctions are often graded not b t abrupt A linear transition region is often a better approximation
2
F m (1 )
j j D
C C V m = − Φ0 1 for abrupt
2 1 for graded (linear)
3 n n p m m p Φ = =
Determine the junction capacitance for
3 3 1/ 2 2 1/2 3
2 10 F 0.9 10 2.5 m (1 ) (1 ) 0.64 2 10 F
j j abrupt D
C C V C
− − − −
× = = = × − − − Φ
1/3 3 3 2 1/ 2
2 10 F 1.2 10 2.5 m (1 ) (1 ) 0.64
j j graded D
C C V
− −
× = = = × − − − Φ
Abrupt and graded junctions
2 3 2
0.5 μm F 2 10 m 0.64 V 2.5 V
D j D
A C V
−
= = × Φ = = −
2 3 4
C (fF) Abrupt Graded
D 1
0.6
V
D (V
)
Strongly voltage dependent capacitance However, digital circuits tend to move fast b t hi h d l lt between high and low voltages An equivalent (average) capacitance Ceq can be used The same amount of charges is moved as by the non-linear model Keq is dependent on the grading coefficient m
0 (derived at page 83) j eq eq j D
Q C K C V Δ = = × Δ
Diodes appears in the drain and source areas (affects power and speed) Diodes should always be backward biased For digital design: the dynamic behavior is important A simple model for hand calculations can b d i di it l d i be used in digital design:
eq eq j
In 1925, Julius Edgar Lilienfeld described the first MOSFET structure
U S Patent in 1930
In early 30:es, a similar structure was shown by Oskar Heil
None of them built a working component None of them built a working component The first working MOS-transistor was shown in early 60:es
MOS = ”Metal Oxide Semiconductor”
Polysilicon SiO2 Polysilicon Silicon, doped
Most important device in digital design V d i h Very good as a switch Relatively few parasitics Rather low power consumption High integration density Simple manufacturing Economical for large complex circuits
2
n
Drain current Gate-Source voltage Drain-Source voltage
2
D GS
I V V
n D T GS
= = =
Drain Source voltage Threshold voltage Gain factor (n-channel)
DS T n
V V k = = =
A simple model:
2
Opens a channel VGS must be lager than a threshold VT
D GS T
Gate
T Gate Source Drain
A Switch Circuit Symbol
S G D VGS VGS
Req S G D
Infinite resistance when VGS < VT Req when VGS ≥ VT VT = Threshold voltage
Gate voltage determine the current from drain to source Source connected to lower potential for n-channel devices (often to GND)
Gate
( ) Source connected to higher potential for p-channel devices (often to VDD) Bulk keeps the substrate at a stable potential. If not shown – it is assumed to be connected to the supply/GND.
Gate Drain Source Drain Source Bulk (Body) Drain Source Bulk (Body)
Gate Source Drain
Technology development:
tox
Source
1993: 0.6 um 2003: 65 nm 2013: 18 nm?
The technology is named after the gate length L “Diode area”
N-MOS P-MOS
Deple- tion With Bulk Enhance- ment Enhance- ment Enhance- ment Enhance- ment With Bulk Drain Source Gate Drain Source Gate
2
( ) 2
n D T GS
k I V V = −
0 4 0.6 0 4 0.6 ID (mA) ID (mA) 3
1 2 0.2 0.4 VGS (V)
1 2 0.2 0.4 VGS (V) 3
6 175 10 2 ( ) 2 0.5
D GS
I V − − × = 6 175 10 2 ( ( )) 2 0.5
D GS
I V − − − × =
CMOS = Complementary MOS Static CMOS means complementary
S VGS
Static CMOS means complementary NMOS/PMOS pairs Their gates are always connected pair wise Note that the corresponding voltages (V V V ) for PMOS are
G D D VDS
voltages (VGS, VDS, VT …) for PMOS are negative That is, The PMOS transistor opens when the gate voltage is lower than the source voltage
S G VGS VDS
The substrate is slightly doped (p- for NMOS) There are always free electrons in the substrate T f h l d t tt t th ti h
VGS > VT
To form a channel, we need to attract these negative charges The threshold is when the number of negative and positive charges are equal The value of VT is thus set by the p-doping concentration
p- Depletion Region n+ n+ n-channel
The bulk is most often connected to GND (VDD for PMOS) Negative VSB opens the diode; Not Allowed Positi e V makes it ha de to att act negati e cha ges to
VGS VSB
Positive VSB makes it harder to attract negative charges to the channel That is, the threshold voltage will increase p- n+ n+ p+
Strongly p-doped
F SB F T T
φF = Fermi potential γ increases with the acceptor concentration Low threshold ⇒ Low voltage transistors but they are leaky y y Two threshold voltage technologies can be used for low power
Determine the threshold voltage for a PMOS transistor with the following data: Twice the threshold voltage! 0.4 0.4 2.5 0.3
T SB F
V V V V V V γ φ = − = − = − = ( 2 2 ) 0.4 0.4( 0.6 2.5 0.6 ) 0.79
T T F SB F T T
V V V V V V γ φ φ = + − + − − = = − − − − − − = = −
Twice the threshold for NMOS as well
0.9 0.55 0.6 0.65 0.7 0.75 0.8 0.85
VT (V)
0.85
VT
0.4 0.45 0.5
VBS (V)
VSB
0.45
When VGS is slightly increased Negative charges are attracted
g g A Depletion region is formed
VGS > 0
p- Depletion Region n+ n+
When VGS is increased above VT More negative than positive charges are attracted
VGS > VT
close to the gate (turns into n-type material) A channel is formed (Strong inversion)
p- Depletion Region n+ n+ n-channel
VDS is increased slightly Horizontal E-field from drain to source
VGS > VT
VDS<VGS-VT
A current ID is established
p- Depletion Region n+ n+ n-channel
ID(VDS) has a resistive behavior ID has a linear relation to VGS
VGS > VT
n+ n+
VDS<VGS-VT
D GS
p- Depletion Region n n n-channel
ID is proportional to the vertical E-field
i.e. to the # of charges attracted by the gate voltage VGS
ID is proportional to the horizontal E-field
i.e. to the charge velocity caused by the drain voltage VDS
VGS forms a vertical E-field
p- n+ n+ID VDS establish a horizontal E-field Electron mobility E-field over the c hannel
n D n
I Q W μ ξ μ ξ = = =
# of charges attracted by the gate Less char ges cl
GS T DS
Q V V Q V − ∼ ∼ the drain
DS
V L ξ = ( ' ´ (
)
n n
DS GS T DS D n
V V V k W I k L V C μ = =
From Horizontal E-Field VDS = VGS – VT Strong inversion reached precisely (i.e. VGD = VT)
No channel close to the drain
VGS > VT
VDS=VGS-VT
p- ”VDS /2" n+
n+
Insert VDS = VGS - VT in the linear equation
D n GS T D n GS T DS DS GS T GS T
2
D n GS T n D GS T GS T
The gain factor is
2
´ ( ) 2
n D GS T
k W I V V L = −
' n n
Where the process transconductance parameter is
'
2
= SiO
ε
Note that the gain is dependent on the oxide thickness i.e. the oxide capacitance
n n
2
Permitivity
VGS > VT
VDS=VGS-VT
p- ”VDS /2" n+
n+
VDS > VGS-VT ⇒ Pinch off The effective channel length is modulated by VDS
ID
VGS>VT VDS>VGS-VT
g y
DS
Electrons are injected through the depletion region
D n+ n+ L L´
Pinch off
VDS > VGS - VT
; { ´ } ´ (1 ); 1 (1 )
D DS D DS DS DS
W I L V L L L W W I V V L V L W λ λ λ λ = − ≈ + << − ∼ ∼
2
´ ( ) (1 )
D n GS T DS
W I k V V V L λ = − +
λ = Empirical constant
Widely used model for manual calculations
2 2
´
(
) 2
´ ((
) 2 λ λ ≥ = + < = +
n DS GS T D GS T DS DS DS GS T D n GS T DS DS
k W V V V I V V V L V W V V V I k V V V V L ´ (
) μ γ φ φ = = + +
SB
n n
T T F F
k C V V V Often added to avoid discontinuity
VGS=5V Linear Region
Slope due to
Resistive
ID VGS=3V VGS=4V g Saturation VDS = VGS-VT
channel length modulation
1 2 3 4 5 VDS [V] VGS 3V
Discontinuity (no channel length modulation in linear region )
With channel length modulation
ID
Without channel length modulation
Linear Saturation Id Id VGS VT VGS VT
2
´ (( ) ) 2
DS D n GS T DS
V W I k V V V L = − −
Linear Region VDS<VGS-VT
Long channel device
2
2 ´ ( ) (1 ) 2
n D GS T DS
L k W I V V V L λ = − +
DS GS T
Saturated Region VDS>VGS-VT
( 2 2 )
T T F SB F
V V V γ φ φ = + − + − −
Threshold Voltage
The electron (hole) velocity is related to the mobility ( )
μ
2 2
m 0.038 = Electron mobility Vs m 0.013 = Hole mobility Vs
n p
μ μ = =
Typical values
The mobility is dependent on doping concentration … Often determined empirically Note that the electron mobility is about 3 times higher
The electron (hole) velocity is related to the mobility The velocity is also dependent on the E-field
( ) μ ( ) ξ
The velocity is also dependent on the E-field ( )
ξ
n n
p p
VDS forms a horizontal E-field An increased E-field leads to higher electron velocity However at a critical E field the velocity saturates due
sat
( ) ξ ( ) ξ
However at a critical E-field , the velocity saturates due to collisions with other atoms
5 m
10 for both electrons and holes s
sat
υ ≈
( )
c
ξ
p- n+ n+
Drain VDS establish a horizontal E-field Source
Electrons typically saturates around 1-5 V/μm Example, Determine the maximum non-saturated V for a 0 25 μm technology if:
sat
VDS for a 0.25 μm technology if:
6 V
c DSAT c
6 6
c DSAT c
−
sat
The mobility is not constant when velocity
Constant Velocity
sat = 10 5 m/s
ν
n (m/s)
saturation is reached
Esat ξ DS [V/um] ξ c
The velocity is
sat
n
υ μ ξ = for 1
n n c
μ ξ μ ξ υ ξ ξ ξ = ≤ +
For saturated devices we modify the expression
1 for
c sat c
ξ υ υ ξ ξ + = ≥
We know the gain factor as
W k C 1 1 1 1
n n
DS
W k C L V L μ κ ξ ξ ξ = × × = = + + ×
A factor must be added
DS
V L ξ =
c c
L ξ ξ ×
The E-field
The equation for the linear region is modified to
2
V C W
2
(( ) ) 2 1
DS D GS T DS n
DS c
V C W I V L V L V V ξ μ = × × − − × × +
Small VDS and Large L give
2
( ( ) ( ) ) 2
DS GS T D n S DS
k V V V V V κ = × − × −
A function of VDS
0.5
VGS-VT = 2.5 - 0.43 = 2.07 V
0.4 0.3 0.2
VGS = VDD = 2.5 For both
2.5 0.5 2.0 1.5 1.0 0.1
VDSAT = 0.63 V
ID (mA) ID (mA) 0.6 0.25
quadratic quadratic linear
D (
)
D (
) 0.1 0.2 0.3 0.4 0.5 0.05 0.1 0.15 0.2
0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5
quadratic Velocity saturation neglected Short Channel VGS (V) VGS (V)
0 25 0 6
VDS = VGS - VT
Quadratic ID(VGS) Linear ID(VGS) 0 05 0.1 0.15 0.2 0.25 0.2 0.3 0.4 0.5 0.6 ID (mA) VGS= 2.5 VGS= 2.0 VGS= 1.5 VGS= 2.5 VGS= 2.0 VGS= 1.5 VGS= 1.0 ID (mA) 0.5 1 1.5 2 2.5 0.05 0.5 1 1.5 2 2.5 0.1 VDS (V) VGS= 1.0 Long Channel Short Channel
GS
VDS (V)
The equation is complex
2
n
DS D GS T DS DS c
A first order model of the velocity is
n c sat n c c
1
n c
μ ξ υ ξ ξ = +
Compare to previous model
n
υ μ ξ = 1
n
μ ξ υ ξ ξ = +
2
0.25 μm m 0.038 Vs L μ = = c
ξ
40000 60000 80000 100000
20000 40000 0.5 1
VDS (V)
DS
V L ξ = ×
0.63 V
DSAT
V =
A first order model for the velocity
y saturated region:
2
DSAT DSAT n
GS T DSAT
2 ' min min
D n GS T DS
min
GS T DS DSAT
2 '
(( ) )(1 ) 2 Resistive
DS D n GS T DS DS
V W I k V V V V L λ = − − +
' 2 2
( ) (1 ) Saturated 2
n D GS T DS
k W I V V V L V W λ = − +
'
Ve (( locity saturated ) )(1 ) 2
DSAT D n GS T DSAT DS
V W I k V V V V L λ = − − +
The equation at inside front
'
; ;
SAT DSAT n n
n c c
V k C L υ μ μ ξ ξ = × = =
at inside front page cover
2 ' 2
2
(( ) )(1 ) 2 (( ) )(1 ) 2
DSAT D n GS T DSAT DS DS n
SAT AT D GS T DSAT DS DSAT
V W I k V V V V L V W I V V V V C L V W λ λ μ υ = − − + = × − − + × (( ) )(1 ) 2 (( ) )(1 2
SAT DSAT DSA DSAT D
GS T DS DSAT D SAT
GS T T
V V L V W I C V V V V I C W V V L V λ υ υ λ = × × − − + = × × − + − )
DS
' 6 2 min
0.43 ; 1.5 ; 1.5 ; 0.63 ; 0.375 0.06; 115 10 172.5 / 0 25
T DS GS DSAT n
V V V V V V V V W k A V L λ μ
−
= = = = = = × × =
min
0.25 L
min min
min( , , ) min(1.5 0.43, 1.5, 0.63)
GS T DS DSAT
V V V V V V = − = −
Find Vmin Velocity Saturated region
2 ' 6 in min 2 m
(( ) )(1 ) 2 172.5 10 ((1.5 0.4 0.63 0.63 3) )(1 0.06 1.5) 89.4 2
D n GS T DS D
W I k V V V L I V V A λ μ
−
= − − + = × − − + × =
Model for manual calculations
1.5 2 2.5 x 10
D (A)
Simulated
0.5 1 1.5 2 2.5 0.5 1
VDS (V) ID
VDSAT
0 15
2 V V =
0.63 V
Linear Velocity saturated VDSAT=VGS-VT 1 06V
0.1 0.15
(mA)
D
I 2 V
GS
V = 1.5 V
GS
V = Saturated
DSAT GS T
0.63=VGS-0.43 1.06V VGS-VT
(V)
DS
V 0.5 1 2 1 V
GS
V =
Velocity saturation is less pronounced for PMOS due to lower mobility
I ( A)
VGS = -1.0V VGS = -1.5V V = -2 0V ID (mA)
VGS = -2.0V VGS = -2.5V VDS (V)
min min
ID (A)
Velocity
VDS (V)
V /2 V
Velocity Saturated
Req
Saturated
Req S G D
VDD/2 VDD
7
x 105
3 4 5 6
Req (Ohm)
0.5 1 1.5 2 2.5
1 2
VDD (V)
VDD (V) 1 1.5 2 2.5 NMOS (kΩ) 35 19 15 13 PMOS (kΩ) 115 55 38 31
(Table on Back Cover)
V l it
0.15
(mA)
D
I 2 V
GS
V = Linear Velocity saturated
0.5 0.1
1.5 V
GS
V =
88
D
I A μ =
Saturated
(V)
DS
V 1 2 1 V
GS
V =
Sub threshold region
ln(ID)
The sub threshold drain current have an exponential relation to the gate voltage (compare to bipolar).
1 2 3 VGS [V] VT
p )
Exponential increase of the static power!
GS T T
V V m v ff
I I e
− ×
= ×
ln(ID)
10n 1u 100u 10m
Low VT High Ioff
I I e = ×
1p 100p 1.0 2.0 2.5 0.5 1.5
VGS (V)
High VT Low Ioff
VT
The Drain/Source
p- n+ n+
The Drain/Source Depletion “helps the channel” to strong inversion. The threshold voltage tends to be l
p- n+ n+
lower.
The depletion region increases around the
VDS = 0
increases around the drain when the VDS increase The effect can not be neglected in a short channel device
p- n+ n+
VDS = VDD
VT tends to be lower
p- n+ n+ T
Short Channel
L VT
Long devices have lower leakage
VDS VT
VDD
n+ n+ p+ p+ p+ n+
GND p- n-
p-
VDD
n+ n+ p+ p+ n-
GND
p+ n+
Drain Source Gate
CGD CGS tox
CDB
n+ n+
CG CSB
Bulk Cap. Junction Cap.
Xd
p Overlap Cap.
CDiff = CBot + CSW Drain/Source Diffusion
Bottom
CDiff CBot CSW
Don’t count the wall towards the channel
T
a r d s a n n e l
Bottom
G a t e T C h a n
Side Wall
Don’t count the wall towards the channel into the perimeter
1 / 2
1 (1 )
bottom j j BD BS
C C Area C Area V = × = × −
1 / 3
(1 ) 1 (1 )
sw jsw jsw BD BS
C C Perimeter C Perimeter V φ φ = × = × −
Abrupt junction Graded junction
Cj/Cjsw is dependent on the bulk voltage Cj0 and φ0 are process parameters
Graded junction
Drain Source Gate
Xd
CGS CGD CGB
Leff
Cut off Linear
n+ n+ n+ n+
Saturation
n+ n+
(Table 3-4) To Bulk To Source To Drain Total Gate Cap.
CGCB CGCS CGCD CG Cut off: No channel ⇒ CGC = CGCB
Cutoff COX W L COX W L + 2 C0W Resistive (1/2) COX W L (1/2) COX W L COX W L + 2 C0W Saturation (2/3) COX W L (2/3) COX W L + 2 C0W
Resistive: Channel ⇒ Divide CGC in two parts Saturation: ≈ 2/3 of Channel to source CGD = Cox × W × Xd CGS = Cox × W × Xd
Drain Source Gate
Xd
Cox in F/μm2
Or CGD = Co × W
d
CGS CGD
Leff
CGS = Co × W
Co in F/μm
CGB Co or Xd are overlap process parameters
Cox = 4.6 fF/μm2 W = 0.6μm; Leff = 0.3 μm; CG = Cox W Leff = 4.6×0.6×0.3×10-12 = CG = 0.83 fF
3 4
C (fF)
1 2
0.6
V
D (V
)
Abrupt Graded
(1 ) 1 1 for abrupt and for graded junction 2 3
j j m D
C C V m m = − Φ = =
Replace non-linear capacitance by a large-signal equivalent linear capacitance hi h di ib l h which distribute equal charge
( ) ( )
j j high j low eq eq j D high low
Q Q V Q V C K C V V V Δ − = = = Δ −
See page 83
1 1
[( ) ( ) ] ( )(1 )
g m m m high low eq high low
V V K V V m φ φ φ
− −
− − − − = − − MOS Capacitance Example (0.35)
Drain (Junction) capacitance
C 0 93 fF/
2
C 0 28 fF/ Cj0 = 0.93 fF/ μm2; Cjsw0 = 0.28 fF/μm; Drain area = W x Ls = 0.6 × 0.7 μm2; Keq =1 Cbottom = 0.7×0.6×0.93 = 0.39 fF Csw = (2×0.7+0.6)×0.28 = 0.56 fF Cdiffusion = 0.39 + 0.56 = 0.95 fF
CG = 0.83 fF Cbottom = 0.39 fF
C !
bottom
Csw = 0.56 fF Cdiffusion = 0.39 + 0.56 = 0.95 fF
Compare!
VDD
Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell
VDD
Leaf Cell
VDD
Decoupling C capacitance when there is space left
Resistance in diffusion and contact
SPICE Level 1 (Shichman-Hodges)
Long channels and manual calculations
SPICE Level 2
Physical model. Not accurate for sub micron tech.
SPICE Level 3
“Empirical” model based on “curve matching”
BSIM (Berkeley Short-channel IGFET Model)
Accurate for short channel devices
Parameter NMOS PMOS Discrete (BF 170)
k' 175 uA/V2
50 mA/V2 V 0 50 V 0 60 V 2 V VT 0.50 V
2 V Leff 0.30 um 0.38 um Weff 0.55 um 0.55 um γ 0.58 V1/2
λ 0.05
tox 7.5 nm 7.5 nm Cox 4.6 fF/um2 4.6 fF/um2 Cj0 0.93 fF/um2 1.42 fF/um2 Cjsw0 0.28 fF/um 0.38 fF/um
2 '
(( ) )(1 ) 2 Resistive
DS D n GS T DS DS
V W I k V V V V L λ = − − +
' 2 2 '
( ) (1 ) Saturated Ve 2 (( locitysaturated ) )(1 )
n D GS T DS DSAT
k W I V V V L V W I k V V V V λ λ = − + = − − +
( 2 2 )
T T F SB F
V V V γ φ φ = + − + − −
Threshold Voltage
Ve (( locity saturated ) )(1 ) 2
D n GS T DSAT DS
I k V V V V L λ = − − +
2 ' min
min min
D n GS T DS GS T DS DSAT
T T F SB F
Gate
Capacitance J ti CGD = CGS = W × Cox × Xd
Junction Capacitance
gmVgs go Vgs Vds
GS D m
V I g ∂ ∂ =
gm
gs
go
gs ds
Linear Region Saturat ion
Id Saturation Id Linear
DS D
I g ∂ ∂ =
1 2 3 4 5 VDS [V] ID
VGS VGS
´ ] ) 2 ( ´ [
DS DS T GS n D
V W k V V V V L W k I g = − − ∂ = ∂ = ) ( ´ ] ) 2 ( ´ [
DS T GS n DS DS DS T GS n DS D
n GS GS m
V V V L W k V V V V V L W k V I g V L k V V g − − = ∂ − − ∂ = ∂ ∂ = = ∂ = ∂ =
DS T GS n D
V V W k V V V L W k I g λ − = + − ∂ = ∂ =
2
) ( ´ )] 1 ( ) ( 2 ´ [
D T GS n DS DS T GS n DS D
GS n GS GS m
I V V L W k V V V V L W k V I g V V L k V V g λ λ λ = − = ∂ + − ∂ = ∂ ∂ = − = ∂ = ∂ =
2 2
) ( 2 ´ )] 1 ( ) ( 2 ´ [ ) (