Cadence tools Brandon Rumberg 1
Tools to cover • Creating piecewise linear (PWL) files • OCEAN scripts • Verilog-A 2
Why use PWL files? • Creating arbitrary waveforms in Cadence is tedious & changes are difficult Piecewise linear source Combining sources 3
PWLF Source • PWLF sources read from a piecewise linear file – ‘vpwlf’ in ‘analogLib’ library • The only necessary Note: I’ve had trouble with the PWLF sources in parameter is the the ‘NCSU_Analog_Parts’ library. They seem to file path/name have trouble finding the PWL file at times. So I recommend using the sources in ‘analogLib’ 4
When PWL files are useful • Testing a circuit with a realistic input acquired from elsewhere – Such as a speech recording • Testing chip-level configuration logic – Such as a serial interface that controls parameters/connections within the chip – You can reuse these files to simplify post-fab testing • Performing a sequence of operations in one transient simulation – Particularly when the result of one operation affects the next operation 5
PWL files • PWL files are text files with rows of time/value pairs Time Value 0.00000000e+00 1.50000000e+00 – ‘Time’ and ‘Value’ are 1.17200000e-03 1.50000000e+00 1.17300000e-03 1.50000000e+00 separated by a space 1.27200000e-03 1.50000000e+00 1.27300000e-03 1.50000000e+00 – Each pair is on a 3.35900000e-03 1.50000000e+00 separate line 3.36900000e-03 5.10000000e+00 4.36900000e-03 5.10000000e+00 • Such files can easily be 4.37900000e-03 5.10000000e+00 1.54379000e-01 5.10000000e+00 generated with – Matlab/Octave – Excel (save as txt file) 6
Generating PWL files • Create matrix with ‘time’ in the first column and ‘value’ in the second column • Save using save -ascii <filename> <matrix> • The file extension is arbitrary 7
Notes about PWLF • Cadence seems to read the PWL file at the instance that the schematic is saved – So if you generate a new PWL file, then you need to resave your schematic before starting a new simulation 8
Tips for generating PWL files • Keep in mind that PWL To create a step, you need to specify the point before the will be interpreted by step connecting the dots • To simplify the creation of a bitstream – Define the hold (T) and rise/fall times (tr), then – Write a function that turns a string of bits into the T tr T tr desired waveform 9
Tools to cover • Creating piecewise linear (PWL) files • OCEAN scripts • Verilog-A 10
OCEAN scripts • OCEAN is a simulator scripting language included in Cadence • Can be thought of as – Parametric sweeps on steroids, or – A cross between Matlab and a simulator • OCEAN – Exposes all simulator, graph, and calculator functions – Includes standard programming language functionality • File I/O • for/while loops • if/else branching • User-defined functions (called ‘procedures’) – Lisp syntax 11
An OCEAN of possibility • Circuit comparison – Create one OCEAN testbench and then automatically swap in/out different netlists • Algorithmic circuit tuning – Rather than using parametric sweeps, create an OCEAN script that automatically tunes the circuit • Parameter extraction – Have OCEAN extract the important circuit performance parameters and save them in a file 12
Creating an OCEAN script • The easiest way to get started is to set up an initial simulation in the Virtuoso environment, then ‘Session-Save Script’ 13
Sample OCEAN script Analysis Design variables Simulate and results • Edit the script with a regular text editor • You can run the script using a different circuit by changing the path in design( ) 14
Running an OCEAN script • You can start ocean by typing ocean at the command line • Then by typing load(“<script>.ocn”) • To avoid retyping full commands, use – !<first letters of command> <Enter> – e.g. !l <Enter> will rerun the last script 15
Modifying an OCEAN script • Use simulation result to calculate capacitor value that gives -20dB at high frequency Define design variables as variables so we can work with them Run first with arbitrary starting values Calculate high-frequency gain using standard calculator functions Calculate capacitor scaling to achieve target gain of -20dB (note that exponentials are done with **, not ^) Change the capacitor value based on the results Resimulate 16
Results of previous slide 17
Tools to cover • Creating piecewise linear (PWL) files • OCEAN scripts • Verilog-A 18
Verilog-A • A modeling language for analog simulation • Uses for Verilog-A – Replace transistor-level circuits • Simulate top-level before all circuits are finished • Evaluate top-level impact of circuit nonidealities • Speed up simulation – Modeling non-standard circuit elements 19
Creating a Verilog-A cell • Create a cell as normal, but choose ‘VerilogA- Editor’ for the tool • This creates and opens a Verilog template Note: You can change the default text editor by typing editor=“<editor name>” in the icfb window The default is vi . You may want to change to nedit for a more conventional text editor. 20
Insert your Verilog-A code Input/output terminals Parameters can be defined Define component operation 21
Symbol Creation & Compilation • When you close the editor window, you will be asked if you want to create a symbol for you Verilog-A code – Select ‘yes’ so that it will automatically generate your pins • The code is automatically compiled when you compile – If there is a syntax error you will receive a notification • Next is the symbol generation dialog box shown to the write • Create symbol as usual 22
Insert symbol for Verilog part & run sim 23
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