IEEE EMBEDDED SYSTEMS LETTERS, VOL. 10, NO. 3, SEPTEMBER 2018 73 Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA Farkhanda Syed , Zahid Ullah, and Manish K. Jaiswal used to emulate TCAM’s function. Today’s FPGAs have high Abstract —Static random-access memory (SRAM)-based ternary content-addressable memory (TCAM), an alternative clock rate, large amount of embedded memories called block to traditional TCAM, where inclusion of SRAM improves the RAMs (BRAMs) of reconfigurable nature, and low power con- memory access speed, scalability, cost, and storage density sumption [1]. FPGA is evolving rapidly because of its support compared to conventional TCAM. In order to confidently use for networking-based applications. Also processing cores and the SRAM-based TCAMs in application, an update module specific embedded designs are available on it which makes (UM) is essential. The UM replaces the old TCAM contents with fresh contents. This letter proposes a fast update mechanism for FPGA faster and denser. Hence, performance gap between an SRAM-based TCAM and implements it on Xilinx Virtex-6 native TCAMs and FPGA is becoming narrower with the field-programmable gate array. To the best of authors’ knowl- passage of time [2]. edge, this is the first ever proposal on content-update-module in SRAM-based TCAMs [3]–[5] are better than conventional an SRAM-based TCAM, which consumes least possible clock TCAMs when lookup operation is required. However, when it cycles to update a TCAM word. comes to updating algorithm, no comparison between conven- Index Terms —Field-programmable gate array (FPGA)-based tional TCAM and SRAM-based TCAM is provided till now. content-addressable memory (CAM), SRAM, ternary content- In conventional TCAM, the stored entries are sorted in ascend- addressable memory (TCAM), UE-TCAM, update module (UM). ing order, which does not allow one to reduce the worst case updating latency less than O ( N ). Here N is the total number I. I NTRODUCTION of entries in TCAM [6]. It is understood that search opera- tion and update operation cannot be performed simultaneously; C ONTENT-ADDRESSABLE MEMORY (CAM) is a thus, slow updates retarded the lookup performance in applica- hardware used in a variety of searching-based applica- tions. For example, in IP networking, owing to slow updates, tions. Here, a search key is provided as an input. The CAM buffering of incoming packets is required to avoid packet loss searches the entire memory against the search key concur- during update process. However, it may cause head-of-line rently and returns the address of the matched CAM word at blocking; thus, a large buffer space other than the main packet output. CAM supports all logical values; binary as well as buffer memory is required, which is undesirable for many ternary. The binary logic supported CAMs are called binary applications [6]. CAMs (BiCAMs) while the three-valued logic supported The rest of this letter is arranged as follows. Section II pro- CAMs are called ternary CAMs (TCAMs). In case of TCAM, vides discussion on prior update algorithms for conventional there is a possibility that more than one TCAM word match TCAM and SRAM-based TCAM available in the literature. the search key. In such a case, a priority encoder is required Section III consists of motivations and key contributions of to choose high priority address as a final matched address. the proposed work. Section IV provides explanation of hybrid Due to the parallel searching mechanism, each TCAM cell partitioning. Section V explains the overall architecture of exhibits a separate matching circuitry; thus, TCAM has low modified update module (UM) integrated with FPGA-based bit storage density. Besides, traditional TCAMs are imple- TCAM. Section VI discusses implementation results and per- mentable on application-specific integrated circuit only and formance evaluation. Section VII contains conclusions and has limited configurability. The demand for TCAM to be directions to the future work. denser, reconfigurable, and easy for integration provokes the idea of implementing field-programmable gate array (FPGA)- based TCAM, where static random-access memory (SRAM) is II. P RIOR W ORKS AND D ISCUSSION Manuscript received September 4, 2017; accepted October 21, 2017. Wang et al. [6] tried to provide a consistent policy TCAM Date of publication November 6, 2017; date of current version table during update process. This is to unlock the TCAM table September 7, 2018. This manuscript was recommended for publication by for lookup operation during an update process. However, rules P. Panda. (Corresponding author: Farkhanda Syed.) in a policy are sorted where rules with high priority are placed F. Syed and Z. Ullah are with the Department of Electrical Engineering, CECOS University of IT and Emerging Sciences, Peshawar 25000, Pakistan at lower memory locations; hence, worst case complexity of (e-mail: farkhandasyed15@gmail.com; zahidullah@cecos.edu.pk). updating algorithm still remains O ( N ) where N is the total M. K. Jaiswal is with the Department of Electrical and Electronic Engineering, University of Hong Kong, Hong Kong (e-mail: number of rules. Thus, it costs design complexity and increases manishkj@eee.hku.hk). power consumption. Besides, 15% empty slots are required Color versions of one or more of the figures in this paper are available every time a system undergoes update process; hence, memory online at http://ieeexplore.ieee.org. usage becomes inefficient. Digital Object Identifier 10.1109/LES.2017.2770225 1943-0663 c � 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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