SLIDE 1 Building manycore processor-to-DRAM networks using monolithic silicon photonics
Ajay Joshi†, Christopher Batten†, Vladimir Stojanović†, Krste Asanović‡
†MIT, 77 Massachusetts Ave, Cambridge MA 02139 ‡UC Berkeley, 430 Soda Hall, MC #1776, Berkeley, CA 94720
{joshi, cbatten, vlada}@mit.edu, krste@eecs.berkeley.edu
High Performance Embedded Computing (HPEC) Workshop
23-25 September 2008
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MIT/UCB
Manycore systems design space
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MIT/UCB
Manycore system bandwidth requirements
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Manycore systems – bandwidth, pin count and power scaling
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1 Byte/Flop, 8 Flops/core @ 5GHz Server & HPC Mobile Client
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MIT/UCB
Interconnect bottlenecks
CPU Cache DRAM DIMM Manycore system cores Cache DRAM DIMM Cache DRAM DIMM CPU CPU Interconnect Network Interconnect Network Bottlenecks due to energy and bandwidth density limitations
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Interconnect bottlenecks
CPU Cache DRAM DIMM Manycore system cores Cache DRAM DIMM Cache DRAM DIMM CPU CPU Interconnect Network Interconnect Network Bottlenecks due to energy and bandwidth density limitations Need to jointly
and off-chip interconnect network
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Outline
Motivation Monolithic silicon photonic technology Processor-memory network architecture exploration Manycore system using silicon photonics Conclusion
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Unified on-chip/off-chip photonic link
Supports dense wavelength-division multiplexing
that improves bandwidth density
Uses monolithic integration that reduces energy
consumption
Utilizes the standard bulk CMOS flow
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MIT/UCB
Optical link components
65 nm bulk CMOS chip designed to test various optical devices
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MIT/UCB
Silicon photonics area and energy advantage
Metric Energy (pJ/b) Bandwidth density (Gb/s/μ) Global on-chip photonic link 0.25 160-320 Global on-chip optimally repeated electrical link 1 5 Off-chip photonic link (50 μ coupler pitch) 0.25 13-26 Off-chip electrical SERDES (100 μ pitch) 5 0.1 On-chip/off-chip seamless photonic link 0.25
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Outline
Motivation Monolithic silicon photonic technology Processor-memory network architecture exploration
Baseline electrical mesh topology Electrical mesh with optical global crossbar topology
Manycore system using silicon photonics Conclusion
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Baseline electrical system architecture
Access point per DM distributed across the chip Two on-chip electrical mesh networks
Request path – core access point DRAM module Response path – DRAM module access point core
Mesh physical view Mesh logical view
C = core, DM = DRAM module
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Interconnect network design methodology
Ideal throughput and zero load latency used as
design metrics
Energy constrained approach is adopted Energy components in a network
Mesh energy (Em) (router-to-router links (RRL), routers) IO energy (Eio) (logic-to-memory links (LML))
Flit width Calculate on-chip RRL energy Calculate on-chip router energy Calculate mesh throughput Calculate total mesh energy Calculate energy budget for LML Total energy budget Calculate LML width Calculate I/O throughput Calculate zero load latency
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Network throughput and zero load latency
System throughput limited by on-chip mesh or I/O links On-chip mesh could be over-provisioned to overcome mesh
bottleneck
Zero load latency limited by data serialization
(22nm tech, 256 cores @ 2.5 GHz, 8 nJ/cyc energy budget)
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Network throughput and zero load latency
System throughput limited by on-chip mesh or I/O links On-chip mesh could be over-provisioned to overcome mesh
bottleneck
Zero load latency limited by data serialization
(22nm tech, 256 cores @ 2.5 GHz, 8 nJ/cyc energy budget)
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Network throughput and zero load latency
System throughput limited by on-chip mesh or I/O links On-chip mesh could be over-provisioned to overcome mesh
bottleneck
Zero load latency limited by data serialization
(22nm tech, 256 cores @ 2.5 GHz, 8 nJ/cyc energy budget) OPF:1 OPF:2 OPF:4
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Network throughput and zero load latency
System throughput limited by on-chip mesh or I/O links On-chip mesh could be over-provisioned to overcome mesh
bottleneck
Zero load latency limited by data serialization
On-chip serialization Off-chip serialization
(22nm tech, 256 cores @ 2.5 GHz, 8 nJ/cyc energy budget) OPF:1 OPF:2 OPF:4
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Outline
Motivation Monolithic silicon photonic technology Processor-memory network architecture exploration
Baseline electrical mesh topology Electrical mesh with optical global crossbar topology
Manycore system using silicon photonics Conclusion
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Optical system architecture
Off-chip electrical links replaced with optical links Electrical to optical conversion at access point Wavelengths in each optical link distributed
across various core-DRAM module pairs
Mesh physical view Mesh logical view
C = core, DM = DRAM module
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Network throughput and zero load latency
Reduced I/O cost improves
system bandwidth
Reduction in latency due to
lower serialization latency
On-chip network is the new
bottleneck
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Network throughput and zero load latency
Reduced I/O cost improves
system bandwidth
Reduction in latency due to
lower serialization latency
On-chip network is the new
bottleneck
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Optical multi-group system architecture
Break the single on-chip electrical mesh into several groups
Each group has its own smaller mesh Each group still has one AP for each DM More APs each AP is narrower (uses less λs)
Use optical network as a very efficient global crossbar Need a crossbar switch at the memory for arbitration
Ci = core in group i, DM = DRAM module, S = global crossbar switch
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Network throughput vs zero load latency
Grouping moves traffic
from energy-inefficient mesh channels to energy-efficient photonic channels
Grouping and silicon
photonics provides 10x- 15x throughput improvement
Grouping reduces ZLL in
photonic range, but increases ZLL in electrical range
A B 10x-15x
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Simulation results
Grouping
2x improvement in bandwidth at comparable latency
Overprovisioning
2x-3x improvement in bandwidth for small group count at
comparable latency
Minimal improvement for large group count
256 cores,16 DM Uniform random traffic 256 cores,16 DM Uniform random traffic
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Simulation results
Replacing off-chip electrical with photonics (Eg1x4 Og1x4)
2x improvement in bandwidth at comparable latency
- Using opto-electrical global crossbar (Eg4x2 Og16x1)
8x-10x improvement in bandwidth at comparable latency
256 cores,16 DM Uniform random traffic 256 cores 16 DM Uniform random traffic
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Outline
Motivation Monolithic silicon photonic technology Processor-memory network architecture exploration Manycore system using silicon photonics Conclusion
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MIT/UCB
Simplified 16-core system design
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MIT/UCB
Simplified 16-core system design
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MIT/UCB
Simplified 16-core system design
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MIT/UCB
Simplified 16-core system design
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MIT/UCB
Simplified 16-core system design
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MIT/UCB
Full 256-core system design
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Outline
Motivation Monolithic silicon photonic technology Processor-memory network architecture exploration Manycore system using silicon photonics Conclusion
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Conclusion
On-chip network design and memory bandwidth will
limit manycore system performance
Unified on-chip/off-chip photonic link is proposed to
solve this problem
Grouping with optical global crossbar improves
system throughput
For an energy-constrained approach, photonics
provide 8-10x improvement in throughput at comparable latency
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MIT/UCB
Backup
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MIT Eos1 65 nm test chip
Texas Instruments
standard 65 nm bulk CMOS process
First ever photonic
chip in sub-100nm CMOS
Automated
photonic device layout
Monolithic
integration with electrical modulator drivers
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MIT/UCB Ring modulator Paperclips Waveguide crossings M-Z test structures Digital driver 4 ring filter banks Photo detector Two-ring filter One-ring filter Vertical coupler grating
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Optical waveguide
Waveguide made of polysilicon Silicon substrate under waveguide etched away to
provide optical cladding
64 wavelengths per waveguide in opposite directions
SEM image of a poly silicon waveguide Cross-sectional view of a photonic chip
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Modulators and filters
2nd order ring filters used Rings tuned using sizing and heating
Resonant racetrack modulator Double-ring resonant filter
Modulator is tuned using charge injection Sub-100 fJ/bit energy cost for the modulator driver
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Photodetectors
Embedded SiGe used to create photodetectors Monolithic integration enable good optical coupling Sub-100 fJ/bit energy cost required for the receiver
