Breaking down Complexity for reliable System-level Timing - - PDF document

▶
breaking down complexity for reliable system level timing
SMART_READER_LITE
LIVE PREVIEW

Breaking down Complexity for reliable System-level Timing - - PDF document

Jan 23, 2023 232 likes •379 views

Breaking down Complexity for reliable System-level Timing Validation Dirk Ziegenbein INSTITU TE OF Marek Jersak COMPUTER AND Kai Richter COMMUNICATION NETWORK ENGINEERING Rolf Ernst Technical University of Braunschweig, Germany Marek

slide-1
SLIDE 1

1

Marek Jersak, TU Braunschweig 1

Breaking down Complexity for reliable System-level Timing Validation

Dirk Ziegenbein Marek Jersak Kai Richter Rolf Ernst

INSTITU TE OF COMPUTER AND COMMUNICATION NETWORK ENGINEERING

Technical University

  • f Braunschweig, Germany

Marek Jersak, TU Braunschweig 2

Outline

  • Complexity of embedded systems
  • Current limitations for timing validation
  • Proposed methodology
  • Breaking down system complexity
  • Single process analysis
  • Single resource analysis
  • Combining results
  • Conclusion
slide-2
SLIDE 2

2

Marek Jersak, TU Braunschweig 3

Embedded System Design

Industry Needs

  • High performance, low cost, low power

Specialized languages, optimized architectures

  • More and more features, short time-to-

market

Platform-based design, application and architecture reuse, IP integration

System size and heterogeneity result in huge system complexity

Marek Jersak, TU Braunschweig 4

Legacy Code Language 1 Language 2

Application Complexity

  • Multi-language design, e.g. Dataflow (voice

processing), FSMs (protocol), legacy code

  • Complex dependencies (contexts, scenarios)
slide-3
SLIDE 3

3

Marek Jersak, TU Braunschweig 5

System Software

Architecture Complexity

  • Heterogeneous platforms and SoC
  • Complex on-chip and distributed networks

platform HW architecture

VLIW

MEM

IP IP

MEM CoPro

RISC

MEM

DSP

SYSTEM BUS

  • System software (RTOS, drivers)

Marek Jersak, TU Braunschweig 6

Integration Complexity

  • Heterogeneous component and language

integration [VSIA, Accellera]

Legacy Code Language 1 Language 2

VLIW

MEM

IP IP

MEM CoPro

RISC

MEM

DSP

SYSTEM BUS

slide-4
SLIDE 4

4

Marek Jersak, TU Braunschweig 7

Timing Validation Complexity

Legacy Code Language 1 Language 2

VLIW

MEM

IP IP

MEM CoPro

RISC

MEM

DSP

SYSTEM BUS [ ] [ ] [ ] [ ] [ ] [ ]

  • Process execution time intervals
  • Complex run-time interdependencies

Marek Jersak, TU Braunschweig 8 Worst-case execution time low bus load

  • System performance corner cases different

from component performance corner cases

SYSTEM BUS

RISC

Best-case execution time high bus load

Limits of Simulation-based Validation

  • Simulation limited to problems with known

corner cases or when full coverage is feasible

slide-5
SLIDE 5

5

Marek Jersak, TU Braunschweig 9

Reliable vs. Unreliable Timing Validation

eliable Architectural Complexity Application Complexity unreliable timing validation reliable timing validation Complex Heterogeneous Platforms & SoCs Single Process Single Resource Homogeneous Multiprocessor TDMA + Static priorities Complex Heterogeneous Platforms & SoCs A B C P1 P2 P3 P4 RMA TTP EDF BB segment pipeline cache Single Process B C A A P1 P2 P3 P4 single processes Single Resource A B C single resources

Marek Jersak, TU Braunschweig 10

Single-Process Timing Analysis

Separation of path analysis and architecture modeling

  • Mok, Puschner, Park (Iteration bounds for loops)
  • Gong and Gajski (Branching probabilities)
  • Li and Malik (Implicit path enumeration)
  • Ye, Wolf, Ernst (Segment-based analysis)
  • First commercial approaches (AbsInt)
slide-6
SLIDE 6

6

Marek Jersak, TU Braunschweig 11

Single-Resource Timing Analysis

Separation of scheduling strategy and activation static priority scheduling

  • Rate-monotonic analysis

e.g. [Liu/Lay73]

  • activation: jitter, burst, etc.

e.g. [Spr89, Tin94]

  • arbitrary deadlines (buffering)

e.g. [Leh90]

dynamic priority scheduling

  • earliest deadline first (EDF)

e.g. [Liu/Lay73]

time driven scheduling

  • time division multiple access (TDMA)

[Kop93]

  • round robin

Marek Jersak, TU Braunschweig 12

eliable Architectural Complexity Application Complexity unreliable timing validation reliable timing validation

Idea: Combine Reliable Results

Complex Heterogeneous Platforms & SoCs A B C P1 P2 P3 P4 Single Process B C A A P1 P2 P3 P4 single processes Single Resource A B C single resources

slide-7
SLIDE 7

7

Marek Jersak, TU Braunschweig 13

P1 P2 P3 P4

1

Application abstraction

  • Processes communicate

via channels

  • Externally visible behavior

(activation conditions, amount

  • f communicated data)
  • SPI [CODES’00, ICCAD’00, DAC’01]
  • Capture multi-language specifications into

homogeneous representation

  • [Simulink - ISSS’01, SDL - CODES’02]

Mapping, scheduling decisions

System Representation

A B C

1

Marek Jersak, TU Braunschweig 14

4 2

B C A A P1 P2 P3 P4 single processes A B C P1 P2 P3 P4

[ ] [ ] [ ] [ ]

Breaking Down Application Complexity

[ ] [ ] [ ] [ ]

3

2 Process interaction abstraction

  • contexts

4 Back-annotation 3 Single-process analysis

  • execution time intervals
  • communication intervals
slide-8
SLIDE 8

8

Marek Jersak, TU Braunschweig 15

Breaking Down Architecture Complexity

5

[ ] [ ] [ ]

A B

[ ]

C P1 P2 P3 P4

5 Resource interaction abstraction

A B C

Marek Jersak, TU Braunschweig 16

Event Models

Available timing-analysis techniques require activation abstraction into event models

periodic with jitter J J J T T periodic with burst T b t b t periodic T T sporadic xt xt xt

slide-9
SLIDE 9

9

Marek Jersak, TU Braunschweig 17

A B C

6

Single-Resource Analysis

5

[ ] [ ] [ ]

A B

[ ]

C P1 P2 P3 P4

6 Single-resource analysis

EMA

[ ]

EMAB EMA‘

Generates

  • Worst/best-case

response times

  • Output event

models

Requires

  • input event models
  • core execution time

intervals

Marek Jersak, TU Braunschweig 18 priority

P1

T1 T1 T1

tresponse tresponse tresponse tresponse

T2 T2

P2

tresponse tresponse tresponse

T3

P3

tresponse tresponse

Given: Periodic input events with period Tx ,

Core Execution Times

Example: Static Priority Scheduling

Response: Periodic with jitter

slide-10
SLIDE 10

10

Marek Jersak, TU Braunschweig 19

5 7

A

[ ]

B

[ ]

C

[ ]

6

Propagation of Event Models

[ ] [ ] [ ]

A B

[ ]

C P1 P2 P3 P4

EMAB EMA

  • Output event models serve as input event

models for analysis of the next resource 8

8

EMAB

EMBC EMBC EMC

7 Back-annotation

EMAB EMA‘

[ ] [ ] [ ]

6 8

  • Iterate steps , and

7

Marek Jersak, TU Braunschweig 20

RISC

P 2 P 3 P 1

RISC

P 4

analysis result: periodic (T) with jitter (J)

Event Model Interface

[Sprunt’89] [Sprunt’89] assumes sporadic input events (t)

t = T - J

Event Model Interface

x t x t x t x t T T T J J

slide-11
SLIDE 11

11

Marek Jersak, TU Braunschweig 21

RISC

P 2 P 3 P 1

RISC

P 4

analysis result: periodic (TX) with jitter (J)

Event Adaptation Function (EAF)

rate monotonic analysis [Liu/Lay73] RMA: assumes periodic input (TY)

?

EAF: timed buffer EMIF TY= TX derive properties of EAF from event models:

  • required buffer size: 1
  • maximum buffering delay: TX

Marek Jersak, TU Braunschweig 22

unreliable timing validation reliable timing validation Reliable timing validation Architectural Complexity Application Complexity

Everything Together

Complex Heterogeneous Platforms & SoCs

[ ] [ ] [ ]

A B

[ ]

C P1 P2 P3 P4 Single Process Single Resource

[ ] [ ] [ ]

B

[ ]

C A A P1 P2 P3 P4 single processes A

[ ]

B

[ ]

C

[ ]

EMAB EMAB

single resources

EMAB

EMA

8 5 7 6 2 4 3 1

EMBC

EMBC EMBC EMC EMA ‘

[ ] [ ] [ ]

slide-12
SLIDE 12

12

Marek Jersak, TU Braunschweig 23

Breaking down Complexity for reliable System-level Timing Validation

Dirk Ziegenbein Marek Jersak Kai Richter Rolf Ernst

INSTITU TE OF COMPUTER AND COMMUNICATION NETWORK ENGINEERING

Technical University

  • f Braunschweig, Germany

Marek Jersak, TU Braunschweig 24

Conclusion

  • Ever increasing embedded system complexity
  • System-level validation not reliable with

current simulation-based techniques

  • Reliable approaches exist for single-process

and single-resource analysis

  • Simple rules to couple single-process and

single-resource analysis techniques

  • Together enables reliable system-level timing

validation of complex embedded systems

slide-13
SLIDE 13

13

Marek Jersak, TU Braunschweig 25

Send(c2,a[j]) a[j]>lim j++ j=1

if for

j<15

  • Execution of

segments to obtain cost intervals (execution time, communication ...)

  • Conservative

combination considering state of pipeline, cache ...

Single-Process Timing Analysis (SYMTA)

  • Analysis of control structures (path classification)
  • Obtain execution number interval for each path

1 15 14 [0,14] 14

1

Marek Jersak, TU Braunschweig 26

Coordination abstraction

  • capture relative rates and

data-dependencies into dataflow representation

  • relax timing constraints

Application Capture: Example Simulink

B1 ts =1 B4 ts=4 B3 ts =3 B2 ts =2

  • Coordination model: Time-driven, idealized

timing

B1 B3 B2 B4

tsim 0 1 2 3 4 5 6 7 8 9

Host model

  • Use RTW to generate

C-code

  • Use target-specific

compiler