Body Effect (Back Bias) Body Effect (Back Bias) Drain 2 qN 2 - - PowerPoint PPT Presentation

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Short Channel MOS Transistor

Professor Chris H. Kim

University of Minnesota

• Dept. of ECE

chriskim@umn.edu www.umn.edu/~chriskim/

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Remember the Standard Vt Equation?

• x

B si a B fb t

C qN V V ψ ε ψ 2 2 2 + + =

• Detailed derivation given in Taur’s book
• Basically, three terms

– Flat band voltage – 2ψB: the magic number for on-set of inversion – Oxide voltage

• Y. Taur, T. Ning, Fundamentals of Modern VLSI Devices,

Cambridge University Press, 2002.

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Body Effect (Back Bias)

• x

sb B si a B fb t sb

• x

sb B si a sb B fb t

• x

B si a B fb t

C V qN V V V C V qN V V V C qN V V + + + = − + + + + = + + = ψ ε ψ ψ ε ψ ψ ε ψ 2 2 2 2 2 2 2 2 2

• Body effect degrades transistor stack performance
• However, we need a reasonable body effect for post silicon

tuning techniques

• Reverse body biasing, forward body biasing

Drain Gate Source Body +

• Vsb

Vsb > 0 : RBB Vsb < 0 : FBB

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Body Effect (Back Bias)

• Vt can be adjusted by applying FBB or RBB

– Essential for low power and high performance – Will talk about body biasing extensively later on

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1 2 3 4 5 6 0.925 1 1.075 1.15 1.225 Normalized frequency Normalized leakage 0% 20% 40% 60% 80% 100% Die count

NBB ABB Accepted dies:

0% 110C 1.1V

Body Biasing for Process Compensation

NBB ABB

Body bias: controllability to Vt

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Short Channel Effect: Vt roll-off

• Ability of gate & body to control channel charge diminishes

as L decreases, resulting in Vt-roll-off and body effect reduction

n+ poly gate p-type body n+ source n+ drain

Short Channel

n+ source n+ drain n+ poly gate p-type body

Long Channel

depletion

Ec Ec Charge sharing Charge sharing

Vt Leff

3σ L variation

• 3σ Vt variation increases in short channel devices

Short Channel Effect: Vt roll-off

8 n+ source n+ drain n+ poly gate p-type body

Long Channel

• Increase in VDS reduces Vt and increases Vt-roll-off: DIBL

n+ poly gate p-type body n+ source n+ drain

Short Channel

depletion

Short Channel Effect: Drain Induced Barrier Lowering (DIBL)

Ec Ec Vds ↑ Vds ↑

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Vt Leff

DIBL+Vt roll-off (Vds=Vdd) Vt roll-off (Vds~0V)

Short Channel Effect: Drain Induced Barrier Lowering (DIBL)

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• DIBL coefficient
• DIBL increases leakage current
• Dynamic Vdd can reduce leakage because of DIBL

Short Channel Effect: DIBL

Vgs (NMOS) Vgs (PMOS) log(Ids) log(Ids)

ds t d

V V Δ Δ = λ

Vds=0.1V Vds=2.0V

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Short Channel Vt Equation

7 . 2 2

) 9 . 2 )( 15 . )( 012 . ( 2 . 2

− −

⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ + + + = m X m W m T m L

j sd

• x

d

μ μ μ μ λ L X X W

j j b

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − + − = 1 2 1 1 λ [Poon, IEDM, 1973] [Ng, TED, 1993]

• x

B si a B fb t

C qN V V ψ ε ψ 2 2 2 + + =

(Long channel Vt equation)

ds d sb B s a

• x

b B fb t

V V qN C V V λ ψ ε λ ψ − + + + = ) 2 ( 2 2

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Transistor Scaling Challenges - Xj

0.4 0.5 0.6 0.7 0.8 50 100 150 200 Junction Depth (nm) IDN (mA/ μm) 0.1 0.2 0.3 0.4 0.5 IDP (mA/ μm) NMOS PMOS 0.05 0.1 0.15 0.2 50 100 150 200 Junction Depth (nm) LMET ( μm) 90 100 110 120 130 R EXT ( Ω μm) LMET REXT RC RSE Rsalicide Salicide Poly-Si Salicide

• S. Asai et al., 1997.
• S. Thompson et al., 1998.
• S. Thompson et al., 1998.

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Effect of Series Resistance

(10nm Device)

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Leakage Components

[Keshavarzi, Roy, and Hawkins, ITC 1997]

Gate Source Drain

n+ n+

Bulk

Reverse Bias Diode & BTBT Gate Induced Drain Leakage (GIDL) Gate Oxide Tunneling Punchthrough Weak Inversion Current, Drain Induced Barrier Lowering and Narrow Width Effect

p-sub

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Sub-Threshold Current

• NPN BJT is formed in sub-threshold region
• Only difference with a real BJT is that the base voltage is

controlled through a capacitive divider, and not directly by a electrode

• Like in a BJT, current is exponential to Vbe

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Sub-Threshold Current

( )

( )

) 1 ( 1

2 kT qV mkT V V q B

• x

eff d

ds t gs

e e m q T k C L W I

− −

− − ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = μ

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Sub-Threshold Swing

• Smaller S-swing is better
• Ideal case: m=1 (Cox>>Csub)

– Fundamental limit = 1 * 26mV * ln10 = 60 mV/dec @ RT – Can only be achieve by device geometry (FD-SOI)

• Typical case: m≈1.3

– S = 1.3 * 26mV * ln10 ≈ 80 mV/dec @ RT – At worst case temperature (T=110C), S ≈ 100 mV/dec

• x

dep

C C m dec mV q kT m S + = = 1 , ) ( 10 ln

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Vdd and Vt Scaling

As Vt decreases, sub-threshold leakage increases Leakage is a barrier to voltage scaling Performance vs Leakage: VT ↓ IOFF ↑ ID(SAT) ↑

) ( ) (

3 T GS SAT

• x

eff D

V V C W K SAT I − ∝ υ

2 2

) ( ) (

T GS eff eff D

V V K L W SAT I − ∝

q mkT V eff eff OFF

T

e K L W I

/ 1 −

∝ VGS

VTL VTH

log(IDS)

IOFFL IOFFH

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Vdd and Vt Scaling

• Vt cannot be scaled indefinitely due to increasing leakage

power (constant sub-threshold swing)

• Example

CMOS device with S=100mV/dec has Ids=10μA/μm @ Vt=500mV Ioff=10μA/μm x 10-5 = 0.1 nA/μm Now, consider we scale the Vt to 100mV Ioff=10μA/μm x 10-1 = 1 μA/μm Suppose we have 1B transistors of width 1μm Isub=1μA/μm x 1B x 1μm = 100 A !!

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Gate Oxide Tunneling Leakage

0 2 4 6 8 10 12

Gate Voltage (V)

10-7 103 100 7 6 5 4 3 2 2 3 2.5nm 3.0nm 3.5nm 5.1nm 7.6nm

• C. Hu, 1996.

IGATE (A/cm2) IOFF IGATE N+ Gate e- P- Substrate

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Gate Oxide Tunneling Leakage

• Quantum mechanics tells us that there is a finite

probability for electrons to tunnel through oxide

• Probability of tunneling is higher for very thin
• xides
• NMOS gate leakage is much larger than PMOS
• Gate leakage has the potential to become one of

the main showstoppers in device scaling

• x

t dd

• x

E B

• x

gate

t V V E e AE I

• x

− = =

−

,

2

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Band-to-Band Tunneling Leakage

EC EC EV EV

p(+)-side n(+)-side

q(Vbi+Vapp)

S/D junction BTBT Leakage

• Reversed biased diode band-to-band tunneling

– High junction doping: “Halo” profiles – Large electric field and small depletion width at the junctions

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Gate Induced Drain Leakage (GIDL)

• Appears in high E-field region under gate/drain
• verlap causing deep depletion
• Occurs at low Vg and high Vd bias
• Generates carriers into substrate from surface

traps, band-to-band tunneling

• Localized along channel width between gate and

drain

• Thinner oxide, higher Vdd, lightly-doped drain

enhance GIDL

• High field between gate and drain increases

injection of carriers into substrate

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Narrow Width Effect

Vt W

Channel

Gate Side view of MOS transistor Extra depletion region

• Depletion region extends
• utside of gate controlled

region

• Opposite to Vt roll-off
• Depends on isolation

technology

width

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Leakage Components

[IEEE press, 2000]