Automating the Area-Delay Trade-off Problem Haven Skinner, Rafael - - PowerPoint PPT Presentation

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Automating the Area-Delay Trade-off Problem Haven Skinner, Rafael - - PowerPoint PPT Presentation

Dec 16, 2022 343 likes •512 views

Automating the Area-Delay Trade-off Problem Haven Skinner, Rafael Possignolo, Jose Renau CARRV 2018 Skinner, Possignolo, Renau 1 Area-Delay Trade-off Problem Fast clock speed Many registers More area/power usage Slow

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SLIDE 1

CARRV 2018

Skinner, Possignolo, Renau

Automating the Area-Delay Trade-off Problem

Haven Skinner, Rafael Possignolo, Jose Renau

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SLIDE 2

CARRV 2018

Skinner, Possignolo, Renau

Area-Delay Trade-off Problem

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  • Fast clock speed

○ Many registers ○ More area/power usage

  • Slow clock speed

○ Save on area/power with fewer registers

  • Difficult to share code
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SLIDE 3

CARRV 2018

Skinner, Possignolo, Renau

Fluid Pipelines

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  • Type of latency insensitive (LI) system
  • Fluid pipeline transformations

○ Add/remove registers ○ Change timing without changing behavior ○ No throughput loss ■ Lax ordering guarantee Elastic Buffer

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SLIDE 4

CARRV 2018

Skinner, Possignolo, Renau

Goal

  • Implement RISC-V architectures with Fluid Pipelines
  • Investigate the viability of Fluid Pipeline transformations as a synthesis tool

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SLIDE 5

CARRV 2018

Skinner, Possignolo, Renau

Fluid Pipeline Transformations

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  • Correct by construction

○ No latency assumptions ○ Decouple behavior from timing

  • Recycling and Retiming

Recycling Retiming

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SLIDE 6

CARRV 2018

Skinner, Possignolo, Renau

Fluid Pipeline Transformations

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  • Merge operation

○ Two stages of a pipeline: merge(s1, s2) ○ Forward and back connections ○ Not commutative: merge(s1, s2) ≠ merge(s2, s1) ■ Behavior is the same ■ Timing may be different

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SLIDE 7

CARRV 2018

Skinner, Possignolo, Renau

Fluid Pipeline Transformations

  • Effect

○ Removes registers ○ CPI decreased ○ Potentially lengthen the critical path

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SLIDE 8

CARRV 2018

Skinner, Possignolo, Renau

Cliff CPUs

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  • Four and five stage RISC-V 64i CPUs

○ c4 - 4-stage Cliff ○ c4+fwd - 4-stage Cliff with forwarding path (dotted line) ○ c5 - 5-stage Cliff Cliff 4-stage Cliff 5-stage

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SLIDE 9

CARRV 2018

Skinner, Possignolo, Renau

Cliff CPUs

  • Transform to 2 and 3 stage cores
  • Compare against others with similar features

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Cliff 4-stage Cliff 5-stage

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SLIDE 10

CARRV 2018

Skinner, Possignolo, Renau

Cliff CPUs (Transforming)

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Cliff 3-stage Cliff 2-stage Cliff 2-stage (alt)

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SLIDE 11

CARRV 2018

Skinner, Possignolo, Renau

Evaluation

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SLIDE 12

CARRV 2018

Skinner, Possignolo, Renau

Area/Delay Pareto

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SLIDE 13

CARRV 2018

Skinner, Possignolo, Renau

Comparison to ARM Cortex-M

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SLIDE 14

CARRV 2018

Skinner, Possignolo, Renau

Conclusion

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  • Fluid pipeline transformations

○ Change timing while maintaining behavior ○ Code reuse

  • So far only the merge operation

○ More transformations can allow for better tuning ○ Long term goal: frequency slide bar

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SLIDE 15

CARRV 2018

Skinner, Possignolo, Renau

Conclusion

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  • Other applications

○ Design space exploration ○ Fast simulation ○ SAT solver-based verification

  • MASC Lab at UC Santa Cruz

○ Fluid pipeline based architecture toolchain ○ Leverage Transformations