Automating the Area-Delay Trade-off Problem Haven Skinner, Rafael - PowerPoint PPT Presentation

Automating the Area-Delay Trade-off Problem Haven Skinner, Rafael Possignolo, Jose Renau CARRV 2018 Skinner, Possignolo, Renau 1

Area-Delay Trade-off Problem ● Fast clock speed ○ Many registers ○ More area/power usage ● Slow clock speed ○ Save on area/power with fewer registers ● Difficult to share code CARRV 2018 Skinner, Possignolo, Renau 2

Fluid Pipelines ● Type of latency insensitive (LI) system ● Fluid pipeline transformations ○ Add/remove registers ○ Change timing without changing behavior ○ No throughput loss ■ Lax ordering guarantee Elastic Buffer CARRV 2018 Skinner, Possignolo, Renau 3

Goal ● Implement RISC-V architectures with Fluid Pipelines ● Investigate the viability of Fluid Pipeline transformations as a synthesis tool CARRV 2018 Skinner, Possignolo, Renau 4

Fluid Pipeline Transformations ● Correct by construction ○ No latency assumptions ○ Decouple behavior from timing ● Recycling and Retiming Recycling Retiming CARRV 2018 Skinner, Possignolo, Renau 5

Fluid Pipeline Transformations ● Merge operation ○ Two stages of a pipeline: merge(s1, s2) ○ Forward and back connections ○ Not commutative: merge(s1, s2) ≠ merge(s2, s1) ■ Behavior is the same ■ Timing may be different CARRV 2018 Skinner, Possignolo, Renau 6

Fluid Pipeline Transformations ● Effect ○ Removes registers ○ CPI decreased ○ Potentially lengthen the critical path CARRV 2018 Skinner, Possignolo, Renau 7

Cliff CPUs ● Four and five stage RISC-V 64i CPUs ○ c4 - 4-stage Cliff ○ c4+fwd - 4-stage Cliff with forwarding path (dotted line) ○ c5 - 5-stage Cliff Cliff 5-stage Cliff 4-stage CARRV 2018 Skinner, Possignolo, Renau 8

Cliff CPUs ● Transform to 2 and 3 stage cores ● Compare against others with similar features Cliff 5-stage Cliff 4-stage CARRV 2018 Skinner, Possignolo, Renau 9

Cliff CPUs (Transforming) Cliff 3-stage Cliff 2-stage Cliff 2-stage (alt) CARRV 2018 Skinner, Possignolo, Renau 10

Evaluation CARRV 2018 Skinner, Possignolo, Renau 11

Area/Delay Pareto CARRV 2018 Skinner, Possignolo, Renau 12

Comparison to ARM Cortex-M CARRV 2018 Skinner, Possignolo, Renau 13

Conclusion ● Fluid pipeline transformations ○ Change timing while maintaining behavior ○ Code reuse ● So far only the merge operation ○ More transformations can allow for better tuning ○ Long term goal: frequency slide bar CARRV 2018 Skinner, Possignolo, Renau 14

Conclusion ● Other applications ○ Design space exploration ○ Fast simulation ○ SAT solver-based verification ● MASC Lab at UC Santa Cruz ○ Fluid pipeline based architecture toolchain ○ Leverage Transformations CARRV 2018 Skinner, Possignolo, Renau 15