Automatic MOSFET Sizing to Maximize the Lifetime Yield of Analog - - PowerPoint PPT Presentation

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Automatic MOSFET Sizing to Maximize the Lifetime Yield of Analog - - PowerPoint PPT Presentation

Feb 03, 2023 302 likes •700 views

Technische Universitt Mnchen Automatic MOSFET Sizing to Maximize the Lifetime Yield of Analog Circuits Husni Habal Technical University of Munich Department of Electrical Engineering and Information Technology The Institute for Electronic

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Technische Universität München

Automatic MOSFET Sizing to Maximize the Lifetime Yield of Analog Circuits

Husni Habal Technical University of Munich Department of Electrical Engineering and Information Technology The Institute for Electronic Design Automation

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Technische Universität München

Contents

  • Overview of the circuit sizing flow
  • Degradation modeling in analog circuits

– Problems and workarounds

– Circuit example

  • Lifetime yield analysis
  • Design centering

– Circuit example

  • Conclusion

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Technische Universität München

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Overview of circuit sizing

Components of the design framework

  • Design centering
  • Lifetime yield analysis
  • Performance simulation
  • Degradation modeling

Design parameters MOSFET width (W), length (L) Operating parameters Temperature (T), Supply (Vdd) Statistical process parameters Threshold voltage (Vth), Toxe Operating time Hours, days, years Parameter degradation , Performances slew rate, gain, power Parametric yield Design centering algorithm Lifetime yield analysis Degradation modeling , Performance simulation

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Technische Universität München

Contents

  • Overview of the circuit sizing flow
  • Degradation modeling in analog circuits

– Problems and workarounds

– Circuit example

  • Lifetime yield analysis
  • Constrained design centering

– Circuit example

  • Conclusion

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Design centering algorithm Lifetime yield analysis Degradation modeling , Performance simulation

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Technische Universität München

Degradation modeling

  • 5

+ _ s d g

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Degradation modeling – analog implementation

  • Differential input stage with cyclostationary analog input
  • Problem: The bias point is not fixed

– – are the node voltages, is the circuit state equation, is an incidence matrix – is periodic with a signal period – the vector of change in all circuit devices

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+

  • Vin

stress+recovery period = 2 hours signal period = 10 µs “Lifetime” = 10 days S S S R R

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Technische Universität München

  • Differential input stage with cyclostationary analog input
  • Solution:

– At small timescales when , (fixed) – Average the Fermi-level dependency over the input period – Recalculate at large time steps to accommodate changes in – Computational cost: a transient simulation for each recalculation

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stress+recovery period = 2 hours signal period = 10 µs “Lifetime” = 10 days S S S R R +

  • Vin

Degradation modeling – analog implementation

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Technische Universität München

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+

  • Vin
  • Differential input stage with realistic cyclostationary analog input

Degradation modeling – analog implementation

Cost: 5 transient simulations

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Technische Universität München

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  • Simulate the effect of degradation on circuit performances

– is the duration needed for calculation of – Performance simulation:

Degradation modeling – performance simulation

Design centering algorithm Lifetime yield analysis Degradation modeling , Performance simulation

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Technische Universität München

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+

  • Vin
  • Simulate the effect of degradation on circuit performances

– is the duration needed for calculation of – Performance simulation:

  • Example: simulate step response to calculate settling time

Degradation modeling – performance simulation

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Technische Universität München

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Degradation modeling – performance simulation

  • Simulate the effect of degradation on circuit performances

– is the duration needed for calculation of – Performance simulation:

  • Problem: need to model degradation during performance simulation ( )

+

  • Vin
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Technische Universität München

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Degradation modeling – performance simulation

  • Simulate the effect of degradation on circuit performances

– is the duration needed for calculation of – Performance simulation:

  • Problem: need to model degradation during performance simulation ( )
  • Solution: if , then ;

; the flow becomes

  • [Habal and Graeb, ICICDT2013]

Design centering algorithm Lifetime yield analysis Degradation modeling Performance simulation

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Technische Universität München

Contents

  • Overview of the circuit sizing flow
  • Degradation modeling in analog circuits

– Problems and workarounds

– Circuit example

  • Lifetime yield analysis
  • Design centering

– Circuit example

  • Conclusion

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Design centering algorithm Lifetime yield analysis Degradation modeling Performance simulation

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Technische Universität München

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Circuit example

  • 45 nm tech [pdk.cadence.com]
  • 39 process parameters
  • 33 design parameters
  • NBTI and HCI modeled
  • Operating parameter ranges
  • Sized without considering degradation
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Circuit example

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Technische Universität München

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Circuit example

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  • Operating parameter dependency

– – Need to consider the worst-case

  • perating corner for degradation:

Open loop Gain

Circuit example

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Technische Universität München

Contents

  • Overview of the circuit sizing flow
  • Degradation modeling in analog circuits

– Problems and workarounds

– Circuit example

  • Lifetime yield analysis
  • Design centering

– Circuit example

  • Conclusion

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Design centering algorithm Lifetime yield analysis Degradation modeling Performance simulation

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Technische Universität München

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  • Gaussian distribution of statistical parameters with mean and covariance

Fresh yield analysis [Graeb 2007]

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  • Gaussian distribution of statistical parameters with mean and covariance
  • Tolerance box for the operating parameters

Fresh yield analysis [Graeb 2007]

T Vdd

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  • Fresh yield analysis:
  • Bijective mapping bwtween and yield:
  • Fresh yield analysis [Graeb 2007]

T Vdd

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1 2 3 4 15.9% 50% 84.1% 97.7% 99.9% 99.99%

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  • Extend the domain of operating parameters with a circuit lifetime
  • Lifetime yield analysis becomes
  • Incremental cost is the cost of an additional operating parameter

Lifetime yield analysis

Operating domain

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Technische Universität München

Contents

  • Overview of the circuit sizing flow
  • Degradation modeling in analog circuits

– Problems and workarounds

– Circuit example

  • Lifetime yield analysis
  • Design centering

– Circuit example

  • Conclusion

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Design centering algorithm Lifetime yield analysis Degradation modeling Performance simulation

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  • is a function of the design parameters
  • Design centering formulation
  • Terminate when yield is satisfactory or no new step is possible

Design centering

1 iteration

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Design centering – circuit example

  • 39 process parameters
  • 33 design parameters
  • Operating parameter ranges
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Design centering – circuit example

  • 39 process parameters
  • 33 design parameters
  • Operating parameter ranges
  • Specifications

60 dB < CMRR 80 dB < Gain 1.5 mV < IOV < 1.5 mV 5 V/us < Slew rate 60 dB < PSRR 7 MHz < UGBW

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Design centering – circuit example

  • 39 process parameters
  • 33 design parameters
  • Operating parameter ranges
  • Cost in CPU time (hours)
  • For lifetime yield analysis:

~ 1000 Performance simulations ~ 3000 Degradation simulations Fresh yield

  • ptimization

Lifetime yield

  • ptimization

Performance simulation

1.6 3.7

Degradation modeling

N/A 15.1

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Design centering – circuit example

  • 39 process parameters
  • 33 design parameters
  • Operating parameter ranges
  • Multi-objective optimization

– Yield versus circuit area

none <400 <360 <320 <300 <280 (um2) 20 40 60 80 (%)

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Technische Universität München

Conclusion

  • NBI degradation model suitable for analog circuit design
  • Decoupling of degradation and performance simulation [ICICDT 2013]
  • Simple extension to calculate lifetime yield analysis
  • Demonstration on a circuit example
  • New circuit examples

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Future work

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Technische Universität München

Backup slides

Husni Habal Technical University of Munich Department of Electrical Engineering and Information Technology The Institute for Electronic Design Automation 30

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Significance of lifetime sizing rules

  • Define the feasible region of operation
  • Aid optimization and reduce cost
  • Typically sharp changes in the

performance functions will be avoided

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Background

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Problems

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  • +
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Problems

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New solutions

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New solutions

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New solutions

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Conclusion

  • Flowchart to evaluate a performance indicator as a function of time

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