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Institute for Electronic Design Automation Technische Universitt Mnchen Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits M. Eick , M. Strasser, H. Graeb, U. Schlichtmann Institute for Electronic Design

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Technische Universität München Institute for Electronic Design Automation

Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits

  • M. Eick, M. Strasser, H. Graeb, U. Schlichtmann

Institute for Electronic Design Automation

  • Prof. Dr.-Ing. Ulf Schlichtmann

Technische Universität München

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Technische Universität München Institute for Electronic Design Automation

Overview

  • Motivation: analog placement constraints
  • Generation of hierarchical placement rules
  • Experimental results

– Comparison with industrial tool – Fully differential amplifier

  • Conclusion

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Technische Universität München Institute for Electronic Design Automation

Constraints in Design Flow

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specification structure sizing placement routing analog block sizing constraints placement constraints routing constraints process variations, parasitic devices etc. layout manual mostly automated mostly manual

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Technische Universität München Institute for Electronic Design Automation

Placement Constraints – Device Matching

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  • Device matching:

equal electrical properties

  • Sources of mismatch, e.g.,

− Distance effects (temperature, oxide thickness, ...) − Orientation effects (μ0, skewed doping, ...)

  • Countermeasures

− Same variant and orientation − Parallel connections instead of larger transistors − Spatial proximity

  • Common centroid

same variant common centroid

[Hastings: The Art of Analog Layout’01]

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Technische Universität München Institute for Electronic Design Automation

Placement Constraints - Symmetry

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differential circuits: symmetrical behavior device matching “symmetrical” routing requires “symmetrical” placement

In Ip Op On

[Cohn et al.: Analog Device-Level Layout Automation’94]

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Technische Universität München Institute for Electronic Design Automation

State of the Art

  • Sensitivity analysis

– Parasitic devices → matching, symmetry [Malavasi et al. TCAD’96] – Net sensitivities → matching [Chen et al. IEE Proc. G’92]

  • Graph isomorphism→ symmetry

[Kole et al. ISCAS’94] [Hao et al. ICCCS’04]

  • Building blocks→ matching (sizing) [Massier et al. TCAD’08]
  • Retargeting using hierarchical symmetry

[Bhattacharya et al. ASP-DAC’04]

  • Circuit hierarchy not considered

– Possibly missing constraints – Infeasible for hierarchical placement

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Technische Universität München Institute for Electronic Design Automation

Hierarchical Placement

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Group 5 Group 4 Group 3 Group 2 Group 1

  • Plantage

[Strasser et al., ICCAD’08]

  • Placement generation controlled

by inherent hierarchy

  • Placement constraints within and

among groups − Matching − Symmetry − Proximity

  • Similar approach:

[Lin et al., DAC’08] hierarchy tree

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Technische Universität München Institute for Electronic Design Automation

Overview

  • Motivation: analog placement constraints
  • Generation of hierarchical placement rules
  • Experimental results

– Comparison with industrial tool – Fully differential amplifier

  • Conclusion

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Technische Universität München Institute for Electronic Design Automation

Flow Chart of New Approach

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netlist building blocks symmetry

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Technische Universität München Institute for Electronic Design Automation

Automatic Structure Analysis

  • Structure recognition

− Comparison with building blocks from library − Resolution of ambiguities − [Massier et al. TCAD’08]

  • Symmetry analysis

− Propagation of symmetry- pairs starting from differential pair − similar to [Arsintescu et al. ICCD’96]

simple current mirror differential pair simple current mirror

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Technische Universität München Institute for Electronic Design Automation

Flow Chart of New Approach

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netlist building blocks symmetry constraint graph constraint graph (netlist) constraint graph (building blocks) constraint graph (symmetry)

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Technische Universität München Institute for Electronic Design Automation

Constraint Graph (Symmetry)

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constraint graph (symmetry) c

  • Symmetry pair→

matching constraint (symmetry) device coordinates axis coordinate

  • Symmetry pairs (d,d‘) of same

axis → symmetry constraint

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Technische Universität München Institute for Electronic Design Automation

Constraint Graph (Symmetry)

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constraint graph (symmetry)

  • Symmetry pair→

matching constraint (symmetry)

  • Symmetry pairs (d,d‘) of same

axis → symmetry constraint

  • Elimination of →

complete graph device coordinates axis coordinate

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Technische Universität München Institute for Electronic Design Automation

Constraint Graph

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constraint graph (building blocks) constraint graph (netlist) constraint graph (symmetry) constraint graph proximity constraint matching constraint matching constraint symmetry constraint

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Technische Universität München Institute for Electronic Design Automation

Flow Chart

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netlist building blocks symmetry constraint graph hierarchical placement rules constraint graph (netlist) constraint graph (building blocks) constraint graph (symmetry)

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Technische Universität München Institute for Electronic Design Automation

Conflict Avoidance

  • Priority order TI:
  • 1. Matching constraints

(symmetry)

  • 2. Matching constraints

(building blocks)

  • 3. Proximity constraints

(building blocks)

  • 4. Symmetry constraints
  • 5. Proximity constraints

(netlist)

  • Criteria, e.g., differential principle

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Technische Universität München Institute for Electronic Design Automation

Hierarchy Generation

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MGS3 MGS1 MGS2 SG1 MGB1 PGN1 MGS1 MGS3 MGS2 MGB1 SG1

  • Controlled by priority order TI:
  • 1. Matching constraints

(symmetry)

  • 2. Matching constraints

(building blocks)

  • 3. Proximity constraints

(building blocks)

  • 4. Symmetry constraints
  • 5. Proximity constraints

(netlist)

  • MGS/B: Matching group

(symmetry / building blocks)

  • SG: Symmetry group
  • PGN: Proximity group (netlist)

PGN1

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Technische Universität München Institute for Electronic Design Automation

Overview

  • Motivation: analog placement constraints
  • Generation of hierarchical placement rules
  • Experimental results

– Comparison with industrial tool – Fully differential amplifier

  • Conclusion

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Technische Universität München Institute for Electronic Design Automation

Hierarchy Generation

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Circuit Number of transistors Groups Runtime [s] Number Size Miller1 9 5 2 – 4 (Ø 2,6) 0,14 Example 10 8 2 – 4 (Ø 2,5) 0,17 Fully Differential OTA2 30 19 2 – 5 (Ø 2,5) 0,46 Folded Cascode OTA1 22 17 2 – 3 (Ø 2,2) 0,31 Buffer3 42 21 2 – 14 (Ø 2,9) 0,65

1 [Laker, Sansen: Design of Analog Integrated Circuits 94] 2 [Galdi et al. JSSC’08], 3 [Fisher et al. JSSC’ 87]

  • Runtime of placer ~ group size
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Technische Universität München Institute for Electronic Design Automation

Comparison with Cadence Virtuoso

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10 20 30 40 50 60 I N I N I N I N I N Number of Constraints Miller Example FD OTA FC OTA Buffer I: Cadence Virtuoso Schematic Editor XL; N: New approach Constraints cluster (hierarchical) symmetry (pairs) cluster (devices) same variant alignment

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Technische Universität München Institute for Electronic Design Automation

Experimental Set-up

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sized schematic of fully differential ota hierarchical placement using Plantage [Strasser et al.; ICCAD’08] parasitics extraction (Cadence Assura) post layout simulation (Cadence Spectre) industrial tool: Circuit Prospector of Cadence Virtuoso Schematic Editor new approach automatic routing (Cadence Chip Assembly Router) unconstrained

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Technische Universität München Institute for Electronic Design Automation

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[Galdi & al., JSSC’08] differential pair current mirrors

Schematic of Fully Differential OTA

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Technische Universität München Institute for Electronic Design Automation

Hierarchical Placement Rules of FD OTA

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MGS1

N1 N2 P11 P14 P12 P15 P13 P16 P8 P9 P10 P4 P7 P1 P2 P3 P5 P6 N6 N9 N5 N7 N8 N11 N12 N14 N3 N4 N10

MGS2 MGS3 MGS4 MGS5 MGS6 MGS7 MGS8 MGS9 MGS10

N13

MGB1 MGB2 MGB3 MGB4 MGB5 MGB6 PGB1 SG1 PGN1

differential pair current mirrors MGS/B: Matching group (symmetry / building blocks); SG: Symmetry group; PGB/N: Proximity group (building blocks / netlist)

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Technische Universität München Institute for Electronic Design Automation

Layout and Post Layout Simulation

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perfor- mance unconstr- ained industrial new approach A0 [dB] 72 72 72 f0 [MHz] 22 22 22 Voffset [μV] 140 93

  • 6.6

CMRR [dB] 78 76 110 differential pair current mirrors

Post layout simulation

placement constraints

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Technische Universität München Institute for Electronic Design Automation

Conclusion

  • Generation of hierarchical placement rules

– Structure and symmetry analysis – Assignment of constraints to constraint graph – Generation of hierarchical groups – Constraints within and among groups: matching, symmetry, proximity

  • Experimental results

– Feasible for hierarchical placement approaches – Comprehensive constraint generation – Improved post layout performance

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Thank you!

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Technische Universität München Institute for Electronic Design Automation

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Technische Universität München Institute for Electronic Design Automation

Constraint Assignment (Netlist)

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  • Connections →

proximity constraints (netlist)

  • Beneficial for routing

Constraint Requirement Graph (Netlist) Nodes = Devices Edges = Constraint Requirements Here: Proximity Constraint (Netlist)

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Technische Universität München Institute for Electronic Design Automation

Constraint Assignment (Building Blocks)

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Requirement Graph (Building Blocks)

  • Two transistor blocks →

matching constraints (building blocks)

  • Larger blocks: additional

proximity constraint (building block)

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Technische Universität München Institute for Electronic Design Automation

Conflict Avoidance

Priority order TI: Criteria:

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  • 5. Proximity constr. (netlist)
  • 4. Symmetry constr.
  • 3. Proximity constr. (building b.)
  • 2. Matching constr. (building b.)
  • 1. Matching constr. (symmetry)
  • Differential principle
  • Increasing size
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Technische Universität München Institute for Electronic Design Automation

Generated Placement

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Placement Constraints: alignment common centroid symmetry axis group

differential pair current mirrors

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Technische Universität München Institute for Electronic Design Automation

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Enumeration of placements of fundamental module sets

Hierarchically Bounded Enumeration

M5 M6 M7 CM M1 M2 DP M3 M4 CM DS CORE OPA M8 C

Fundamental module sets

M5 M6 M7 M5 M6 M7 M5 M6 M7

…

M3 M4 M3 M4 M3 M4

…

M8 C M8 C M8 C

…

M1a M2a M2b M1b

…

M2a M1a M1b M2b M5 M6 M7 CM M1 M2 DP M3 M4 CM DS CORE OPA M8 C

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Technische Universität München Institute for Electronic Design Automation

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Enhanced Shape Functions

M5 M6 M7 CM M1 M2 DP M3 M4 CM DS CORE OPA M8 C M5 M6 M7 M5 M6 M7 M5 M6 M7

…

M3 M4 M3 M4 M3 M4

…

M8 C M8 C M8 C

…

M1a M2a M2b M1b

…

M2a M1a M1b M2b

  • Hierarchical approach
  • Good for semi-automatic

layout generation

  • High flexibility
  • Enhanced shape function

for each node of hierarchy

  • Close proximity of modules

is achieved by hierarchy

Enhanced Shape Functions Enhanced Shape Addition