UT DA Hierarchical and Analytical Hierarchical and Analytical Pla - - PowerPoint PPT Presentation

UT DA

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Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, and David Z. Pan ECE Department, University of Texas at Austin ISPD, March 20th, 2017

Hierarchical and Analytical Hierarchical and Analytical Pla Placement T cement Technique echniques for s for High High- Performa Performance A nce Analog C nalog Circuit ircuits

Outline Outline

High-Performance Analog IC Placement Challenges Hierarchical and Analytical Placement Techniques for High-Performance Analog ICs Experimental Results

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Outline Outline

High-Performance Analog IC Placement Challenges Hierarchical and Analytical Placement Techniques for High-Performance Analog ICs Experimental Results

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Analog Analog IC Placement IC Placement

Complicated: 2-dimensional Constraints: symmetry, proximity, etc. Manual placement: low productivity and error-prone

4 Analog IC placement example Bounding box of a placement device a symmetric group, with symmetric pairs and self- symmetric devices

Challenges Challenges

Limitation of existing analog PDA tools: lack of designer involvement

 Capture circuit design intents  Provide insurance  Spread wider use of automation tools

Circuit hierarchy

 Easy to read, debug and control quality

Net-specific criticality

 Conventional objectives of area and HPWL: insufficient for high-performance analog ICs  + Circuit performance: longer running time

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High High-Perfor Performance mance Analog Analog IC IC Exam Example ple 1

Output nodes are critical => delay

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C_OUTN C_OUTP CC_OUT C_XP C_XN C_VG CC_XIP CC_XIN

INP INN CLK CLK CLK OUTP OUTN

VDD GND OUTP OUTN C_OUTN

1 fF 2 fF

C_OUTP

1 fF 2 fF

OUTN OUTP C_VG 0 -> 2 fF

High High-Perfor Performance mance Analog Analog IC Example IC Example 2

CCO output nodes (ring CCO oscillating nodes) are critical => CCO gain => noise shaping performance

• f the ring sampler

7 Buffers Current-Controlled Oscillators (CCOs) Detects phase difference and lead lag status of the 2 CCOs

Prior Prior Works Works

Sensitivity analysis [K. Lampaert+, JSSC’95]

 Exhaustive circuit analysis was time-consuming

Proximity constraints [M. Strasser+, ICCAD’08], [P.-H. Lin+, TCAD’09], [Q. Ma+, TCAD’11]

 Not directly minimize the critical parasitics

Monotonic current paths constraints [P.-H. Wu+, ICCAD’12], fully separation of analog and digital signal paths [P.-H. Lin+, TCAD’16]

 No net-specific criticality consideration

Designer-guided criticality determination + direct critical parasitic minimization are needed!

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Our Our Contr Contributions ibutions

Keep analog designers in the loop Critical parasitics to optimize circuit performance

 Designer-guided  Direct critical net HPWL minimization with analytical approach

Hierarchical placement

 Respects multi-level hierarchical structure of analog ICs  Designer friendliness: intuitive to read and debug

Hierarchical MILP and parallelization

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Outline Outline

High-Performance Analog IC Placement Challenges Hierarchical and Analytical Placement Techniques for High-Performance Analog ICs Experimental Results

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Overall Overall Flow Flow

Hierarchical and Analytical Placement Construct Circuit Hierarchical Structure

Proximity Constraints Critical Nets Hierarchical Symmetry Constraints

Placement Results

Circuit Netlist Information

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Optimizes total area, total HPWL, and critical net HPWL

Cir Circuit cuit Hierarchy Hierarchy Constr Construction uction

Use when the circuit hierarchy is not given Analog circuit partitioning:

 Proximity groups-feasible  Symmetric groups-feasible  Critical parasitics

We integrated these requirements into hMetis

12 hMetis: http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview

Parallelized Parallelized Hierarchical Hierarchical Framework Framework

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Parallelized Parallelized Hierarchical Hierarchical Framework Framework

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Parallelized Parallelized Hierarchical Hierarchical Framework Framework

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Parallelized Parallelized Hierarchical Hierarchical Framework Framework

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Parallelized Parallelized Hierar Hierarchical chical Framework Framework

O(L) with assumptions

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Multi Multi-Objective Objective Optimization Optimization

Symmetric constraints (e.g. vertical symmetric)

 (symmetric pairs) 𝑦𝑗 + 𝑥𝑗 + 𝑦𝑘 = 2 ∗ 𝑦𝑡𝑧𝑛  (self-symmetric) 2 ∗ 𝑦𝑙 + 𝑥𝑙 = 2 ∗ 𝑦𝑡𝑧𝑛

Non-overlapping constraints

 𝑦𝑗 + 𝑥𝑗 ≤ 𝑦𝑘 + 𝑋

𝑛𝑏𝑦 𝜈𝑗𝑘 + 𝜉𝑗𝑘 , 𝑦𝑗 − 𝑥 𝑘 ≥ 𝑦𝑘 − 𝑋 𝑛𝑏𝑦(1 + 𝜈𝑗𝑘 − 𝜉𝑗𝑘)

 𝑧𝑗 + ℎ𝑗 ≤ 𝑧𝑘 + 𝐼𝑛𝑏𝑦 1 − 𝜈𝑗𝑘 + 𝜉𝑗𝑘 , 𝑧𝑗 − ℎ𝑗 ≥ 𝑧𝑘 − 𝐼𝑛𝑏𝑦(2 − 𝜈𝑗𝑘 − 𝜉𝑗𝑘)

Boundary constraints

 𝑦𝑗+𝑥𝑗≤ 𝑋, 𝑧𝑗+ℎ𝑗≤ 𝐼 18 total HPWL Critical net HPWL

min {𝐵, 𝑋𝑀, 𝐷𝑀}

Area, W*H

min {𝑋, 𝐼, 𝑋𝑀, 𝐷𝑀}

1) Optimize H, W, WL and CL sequentially

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Handling Handling Multiple Multiple Objectives Objectives

Constrain W,

• pt. H

Constrain H,

• pt. W

Constrain H, W,

• pt. WL, CL

Handling Handling Multiple Multiple Objectives Objectives (cont (cont.)

2) Fix maximum area and optimize WL and CL 3) Optimize weighted sum of H, W, WL and CL

20 Example of 2) Example of 3)

General General MILP MILP Formulation Formulation

𝛿: critical net weight 𝛽, 𝛾, 𝜄: objectives weights

 Optimize certain objectives by setting others to 0

𝐼0, 𝑋

0, 𝑋𝑀0: Normalization factors

 𝐼0, 𝑋

0 set by desired aspect ratio

 𝑋𝑀0 set to “average” total HPWL, #𝑜𝑓𝑢𝑡 ∗ (𝐼0 + 𝑋

0)/2

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Outline Outline

High-Performance Analog IC Placement Challenges Hierarchical and Analytical Placement Techniques for High-Performance Analog ICs Experimental Results

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Cri Critical tical Parasit Parasitics ics Minimization Minimization

Critical net HPWL decreases by 11.9%, total HPWL increases by 2.8% on average

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Example Example 1: 1: Comparat Comparator Circuit

• r Circuit

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Example Example 2: 2: Ring Sampler Ring Sampler Slice Slice

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Compare Different Compare Different MOO MOO Approaches Approaches

26 𝛿 = 0

Sequential approach: best at optimizing area Fixed area approach: best at optimizing WL and CL

𝛿 = 20

Comparisons Comparisons with Prior Works with Prior Works

[P.-H. Lin+, TCAD’09] does not consider critical parasitics minimization Better quality with run-time overhead

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Summary Summary

Hierarchical and analytical placement techniques for high-performance analog circuits Capture design intents Directly minimize critical net HPWL Hierarchical partitioning Hierarchical MILP formulation for hierarchical placement and parallelization

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Thanks! Thanks!

Q&A

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