ATLAS MDT ASD_V4 Design May 29 th , 2017 Federica Resta Marcello - - PowerPoint PPT Presentation

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ATLAS MDT ASD_V4 Design May 29 th , 2017 Federica Resta Marcello De Matteis andrea.baschirotto@sparklingic.com ASDv4 Outline Channel Block Scheme Charge Sensitive Preamplifier Differential Amplifiers Wilkinson ADC

SLIDE 1

ATLAS MDT ASD_V4

Design

May 29th, 2017

Federica Resta Marcello De Matteis andrea.baschirotto@sparklingic.com

SLIDE 2

ATLAS MDT ASD DESIGN REVIEW 5/26/17 2 of 26

ASDv4

Outline

 Channel Block Scheme   Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC  Measurements Summary  Conclusion

SLIDE 3

ATLAS MDT ASD DESIGN REVIEW 5/26/17 3 of 26

ASDv4

Channel Block Scheme

Fig. 1 – Channel Block Scheme.

SLIDE 4

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ASDv4

Channel Critical Design Points (1/2)

 CMOS Technological Node

130nm
3.3V Supply Voltage
VTH Reduction
0.45V vs 0.75V
Sligth Reduction of intrinsic MOS gain
Smaller Signal
Substrate influenced by rail-to-rail digital signals
Smaller Area

 Detector Parasitic Capacitance

60pF

Required a CAREFUL CSPreamp Design

SLIDE 5

ATLAS MDT ASD DESIGN REVIEW 5/26/17 5 of 26

ASDv4

Channel Critical Design Points (1/2)

 CSPreamp

INPUT and KEY BLOCK
Charge to Voltage Conversion
Essential Matlab Model for performance optimization
Noise
Sensitivity
Peaking Time Delay

 Parasitic Capacitance at CSPremp Output

To guarantee a good conversion speed

SLIDE 6

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ASDv4

Outline

 Channel Block Scheme  Charge Sensitive Preamplifier   Differential Amplifiers  Wilkinson ADC  Measurements Summary  Conclusion

SLIDE 7

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ASDv4

Charge Sensitive Preamplifier

 Pseudo-Differential Structure

2 identical Charge Sensitive

Amplifiers

CSPreamp
CSPreamp Dummy

 Feedback Components:

CF
RF=RF1+RF2

SLIDE 8

ATLAS MDT ASD DESIGN REVIEW 5/26/17 8 of 26

ASDv4

Charge Sensitive Preamplifier

∙
∙
 With
Detector Capacitance (CD)
Feedback Capacitance (CF)
Feedback Resistor (RF=RF1+RF2)
Load Resistor (RL)
DC Loop Gain (gm1∙RL≈400)
CD/CF≈88

SLIDE 9

ATLAS MDT ASD DESIGN REVIEW 5/26/17 9 of 26

ASDv4

Charge Sensitive Preamplifier

∙
∙
 Choosing
RL=RF
gm1>>1/RF

 High Frequency Zero (≈5GHz)  CSPreamp Transfer Function can be approximated to:

∙∙

∙

SLIDE 10

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ASDv4

CSPreamp Dominant Pole

 Ideal Case:

Open Loop Amplifier has
Infinitive gain
Infinitive bandwidth
Ideal Dominant Pole Constant 
Ideal Sensitivity  ,
 Finite DC Gain (gm1∙RL≈400)
Dominant Pole Constant 
Sensitivity 

∙

SLIDE 11

ATLAS MDT ASD DESIGN REVIEW 5/26/17 11 of 26

ASDv4

CSPreamp Second Pole Effect

 Ideal Case:

Open Loop Amplifier has
Infinitive gain
Infinitive bandwidth
Ideal Dominant Pole Constant 
Ideal Sensitivity  ,
 Finite DC Gain (gm1∙RL≈400)
Dominant Pole Constant 
Second Pole Constant 
Sensitivity 

∙

SLIDE 12

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ASDv4

CSPreamp Transient Noise Model

SLIDE 13

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ASDv4

CSPreamp Loop Gain

SLIDE 14

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ASDv4

CSPreamp Frequency Responses

SLIDE 15

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ASDv4

CSPreamp Design Parameters Summary

SLIDE 16

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ASDv4

Outline

 Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers   Wilkinson ADC  Measurements Summary  Conclusion

SLIDE 17

ATLAS MDT ASD DESIGN REVIEW 5/26/17 17 of 26

ASDv4

Differential Amplifiers

Smaller CMFB MOS:  Reduce CSPreamp Parasitic Capacitance Load  Manage Peaking Time Delay

SLIDE 18

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ASDv4

Differential Amplifiers

 5MHz center frequency  30kHz high-pass frequency  +6dB/octave slope

SLIDE 19

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ASDv4

Outline

 Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC   Measurements Summary  Conclusion

SLIDE 20

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ASDv4

Wilkinson ADC

 Gain Stages Optimization

Reduction Parasitic Capacitance
Symmetrical Layout

SLIDE 21

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ASDv4

Outline

 Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC  Measurements Summary  Conclusion

SLIDE 22

ATLAS MDT ASD DESIGN REVIEW 5/26/17 22 of 26

ASDv4

Measurements Summary (1/2)

Fig. 2 – MDT-ASDv4 Chip Photo.
Fig. 3 – DA3 Output Signal vs. Input Charge.
Fig. 4 – Channel Sensitivity vs. Input Charge.
Fig. 5 – Peaking Time Delay vs. Input Charge.

SLIDE 23

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ASDv4

Measurements Summary (2/2)

Fig. 6 – W-ADC, DA3 Output Signals vs. Input Charge.
Fig. 7 – W-ADC Output Pulse Width vs. Input Charge.

SLIDE 24

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ASDv4

Outline

 Channel Block Scheme  Charge Sensitive Preamplifier  Differential Amplifiers  Wilkinson ADC  Measurements Summary  Conclusion 

SLIDE 25

ATLAS MDT ASD DESIGN REVIEW 5/26/17 25 of 26

Fig. 8 – MDT-ASDv4 Pin Table (70 Pins).

ASDv4

Conclusion

 MDT-ASDv4

Management of 60pF-CD
Accurate qIN-to-V conversion
Maximum Peaking Time Delay  12ns
Linear V-to-T conversion
Area of 6.38mm2

1 Including CSP+DA1+DA2+DA3+DA4+DISC1+WILKINSON ADC+MUX+LVDS 2 Including CSP+DA1+DA2+DA3+DA4+DISC1+WILKINSON ADC

Total Current Consumption 162mA Channel1 Current Consumption 18.7mA* Channel2 Current Consumption 12.56mA Total Power Consumption @3.3V of Supply Voltage 535mW Channel1 Power Consumption @3.3V of Supply Voltage 61.9mW Channel2 Power Consumption @3.3V of Supply Voltage 41.44mW

* 32.7% LVDS 21% CSP 20.2% Wilkinson ADC 16% DAii=1,2,3,4 chain 6.5% DISC1

SLIDE 26

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ASDv4

Conclusion – Measurements Issues

1. Substrate Noise
2. Channel Mismatch
3. Smaller Deadtime Range