[PPT] - Asynchronous logical networks II Digital Systems M 1 State PowerPoint Presentation

SLIDE 1

Asynchronous logical networks II

1

Digital Systems M

SLIDE 2

2

State variable coding impact on the behaviour ?

Safe again…. With the last coding..

The transition indicated by the red arrow is very

dangerous. Theoretically from 10 (stable for input 01) with

input 11 the state should switch to 01 (stable – dashed red arrow). But one of the two state variables necessarily switches before the other

1 11 00 01 11 10 00 00

X1 X2

00 11 10 00 00 11 00 10 01 00 10 00 00 01 00 01

Y1 Y2

00 11 00 01 11 10 00 00

00

X1X2

A 00 11 10 00 00 B 11 00 10 01 00 C 10 00 00 01 00 1 D 01

Y1Y2

(Transition table NOT a Karnaugh map)

Z In the case of the green arrow (10->00) Y1 is the first to change and the system reaches the state 00 (wrong !) which is stable with input 11 ! In the case of the blue arrow (10->11) where Y2 switches first the system reaches the state 11 which for 11 input shows a further race (once again a double state change from 11 to 00). If in this case Y2 switches first the system reaches the wanted state 01 (stable) with input 11

therwise

the system goes back to state 10 with a possible

scillation.

Everything depends

n

the combinatorial network delays

A race is a state transition where two ore more state variables must switch concurrently A race is critical if a wrong stable state is reached because of non concurrent state variables change

SLIDE 3

3

In this table we have supposed a double input change which must in any case be avoided

Another (non primitive) state table

N.B. this isn’t the safe

Combined inputs-states effects Karnaugh

blue -> transition Green -> race Red

> stable state

11 00 01 11 10 10 A 00 01 00 00 B 01 00 10 C 10 11 00 11 00 D 11 1

Y2Y1

00 01 01 10 10

X2 X1

Z

1 D 00 01 11 10 A C B

X2 X1

A 00 B A A B B 01 A C C C C 10 D A D A D 11

Y2Y1 Z

1

This table (among other problems) has a critical race. A is stable with input 01. If the input should switch to 10 (double input change) the state to be reached should be B (black solid arrow). In practice there are two possibilities: either X1 switches first or the other way round. If X2 switches first the input transition indicated by the red arrow (00->10->10) occurs leading to to stable state C with 10 ! If X1 switches first the blue transition occurs which in turn can lead to different situations if starting from state A-00 (with input 00 and theoretical destination D-11) either Y1 or Y2 switches first. In the first case it is possible that the wanted final state is reached (violet dashed transition). In the second case (dashed green transition) the system reaches C stable again! It must be noticed that further input or states delays could provoke even different dynamic transitions!!

SLIDE 4

4

How to cope with this situation ?Setting aside the input problems let’s analyse all the races (green)

f the state variables that is all transitions which imply the change of two state variables. The

previous table can be modified. Multiple transitions. In circled orange the modifications Some remarks:

Multiple transitions

are not always possible (more are the stables states in a column more unlikely are multiple transitions)

11 00 01 11 10 10 A 00 01 00 00 B 01 00 10 C 10 11 00 11 00 D 11 1

Y2Y1

00 01 01 10 10

X2 X1

Z Future state change

01

Multiple Transition

10

Multiple Transition

01

Transition change

11

In the first column from C the system should switch to A and then to D. It is therefore possible to switch directly to D. By so doing a multiple transition from A(00) to D(11) (A->C->D) is possible.

In the columns where only a stable state is present it is not necessary to insert

multiple transitions provided no oscillations can occur

Multiple transitions induce network delays

SLIDE 5

5

Let’s consider the safe initial synthesis

01 00 01 11 10 00 00 00

X1X2

00 01 11 00 00 01 00 11 10 00 11 00 00 10 00 1 10

y1y2

Z = Y1 !Y2 Y1 = y1

t+τ = (!x1x2y2 + x1x2y1) t

Y2 = y2

t+τ = (!x1!x2!y1 + !x1x2 y2) t Here we have a race . Theoretically since there is only

ne stable state in the column

no problems should arise but if the variables switching times are different an oscillation is always possible. Better a multiple transition (11->01->00)

Z

SLIDE 6

6

Analysis of this asynchronous sequential circuit (inputs X1,X2 , Reset and output Z)

Detect the state variables and their equations and using the algebra theorems simplify them

indicating what theorems have been used

Detect the state transition table and its problems (if any)
Detect all possible malfunctions and provide a table solving them
Synthesize the initial transition table (after removing the possible races) using SR feedback

SLIDE 7

7

Y1= !(!x1 !x2) (y1 + x1y2) = (x1+x2)(y1+ x1y2)= x1y1 + x1y2 + x2y1 + x1x2y2= = x1y1 + x1y2 + x2y1 Y2 = !(!x2y1 + !(x1x2 + y2)) = !(!x2y1) (x1x2+y2)= (x2 +!y1) (x1x2+y2)= = x1x2 + x1x2!y1 + x2y2 + !y1y2= x1x2 + x2y2 + !y1y2 Z = y1!y2 Idempotence !

Y1 Y2

Leaving aside Reset

SLIDE 8

00,1 L 00,0 01,1 F 11,1 11,0 00,1 A gate system is controlled by two pushbuttons X1 and X2. When closed the gate will be opened only after the sequence 10-00-01 is activated. Once open the gate will remain open until the closure sequence 11-01-11 is activated. Once closed the gate will remain closed and will be opened only when another open sequence is

activated. Design the system with the Mealy model and a primitive state diagram. Once derived the state

variables expressions implement the system in VHDL and by simulation check the correctness of your design inserting the correct and the wrong sequences. Use process and «if» structures in VHDL. 10,0 00,0 00,0 C 01,- 01,1 D 11,1 E 01,1 11,0 G 11,- 11,0 X1X2,Z 00,0 A 01,0 H 01,0 10,0 B 00,1 01,1 L 10,0 10,1 M 10,1 11,1 10,1

VHDL Bidirectional_lock

SLIDE 9

Z = y1!y2

00 00 01 11 10 00 01 00

X1 X2

00 01 01 11 11 01 00 11 11 10 11 00 10 11 10 1 10

y1y2

01 is never stable and reacheable (it can be reached only from state 00 with 11 input BUT is unstable)

9

Y2 = x1x2 + x2y2 + !y1y2 Y1= x1y1 + x1y2 + x2y1

SLIDE 10

00 00 01 11 10 00 01 00

X1X2

00 01 01 11 11 01 00 11 11 10 11 00 10 11 10 1 10

y1y2

In red the only critical race

00 00 01 11 10 00 01 00

X1X2

00 01 01 11 11 01 10 11 11 10 11 00 10 11 10 1 10

y1y2

Table without critical races

10

SLIDE 11

00 00 01 11 10 00 01 00

X1X2

00

11
01

10 11 11 10 11 00 10 11 10 1 10

y1y2

Simplified equivalent table (how must it be modified to insert a don’t care in the only transition leading to the unstable state 01 ?)

Y1 = y2 + X2y1 + X1y1 Y2 = X2y2 + X1X2 S1 = X1y2 R1 = !X1!X2!y2 S2 = X1X2 R2 = !X2y1

00 00 01 11 10 00 01 00

X1X2

00 01 01 11 11 01 10 11 11 10 11 00 10 11 10 1 10

y1y2

Initial table without critical race (zeros red/blue -> R=1 S=0 with black zeros , ones red/blue -> S=1, R=0 with black ones)

11 Removed race

SLIDE 12

12

Incompletely specified state/transition tables

00 00 01 11 10 01 00 10

X2

00 00 01 11 11 01 00 01 11 10 11 00 00 11 10 1 10

y1y2 X1

The green transitions can NEVER occur since two simultaneous inputs changes can never occur …..

Z

00 00 01 11 10 01

10

X2

00 00 01 11

01
01

11 10 11 00

11

10 1 10

y1y2 X1

… and therefore can be substituted with ”don’t care”

Y1=X1 Y2=X2

The network is combinatorial as it could be immediately detected (the stable states coincide with the inputs !!!). A table where each state is stable for only one input configuration is a primitive table

Z

SLIDE 13

13

How is an asynchronous sequential network designed? - 1

1st step: a primitive state diagram must be designed. If for each transition a new state is reached (or inserted) no problem, provided the history of the circuit is correctly interpreted

therwise the state number explodes. It must be understood the time development of

the circuit and to detect the states which correct represent this develooment. There are no algorithms to design the state diagram but the human brain only

Safe again

01,0 01,0 11,1 11,- 01,0 E 10,0 11,0 F 11,0 10,0 01,0 11,0 01,- 10,0 D 10,- 00,0 00,0 00,0 01

Mealy (but could be Moore)

X1X2,Z 00,0 A B C

The

transitions

utputs

are don’t cares since their values are not important (the difference is only WHEN the change occurs)

Primitive table
From C with input

01 the transition is not to B

therwise

the

utput

would be activated without the correct sequence (see circuit history)

The states D,E and F do not belong to the

correct sequence

SLIDE 14

14

A X1X2,Z 00,0 B 01,0 01,0 C 11,1 11,- 01,0 E 10,0 11,0 F 11,0 10,0 01,0 11,0 01,- 10,0 D 10,- 00,0 00,0 00,0

How is an asynchronous sequential network designed? - 2

2nd step: primitive state table (the transition which would imply the change of two inputs variables are don’t cares)

A,0

00 01 11 10

B,0

,-

D,0

X1 X2

A

A,0 B,0 C,-

,-

B

,-

E,- C,1 D,-

C

A,0

,-

F,0 D,0

D

,-

E,0 F,0 D,0

E F

A,0 E,0 F,0

,-

SLIDE 15

15

How is an asynchronous sequential network designed? - 3

3rd step: compatible states detection for the state reduction. Two states are compatibile if, where

specified, for the same inputs they provide the same outputs (where specified) and switch to the same states or to compatible states. Implication triangular table.Two by two

comparison between states. If the outputs (where defined) are different for the same input configuration the states are incompatible. Otherwise in the square the condition (if any) uder which they could be compatible is recorded.

A B C D E B C D E F

A,0

00 01 11 10

B,0

,-

D,0

X1 X2

A

A,0 B,0 C,-

,-

B

,-

E,- C,1 D,-

C

A,0

,-

F,0 D,0

D

A,0 E,0 F,0

,-

E

,-

E,0 F,0

F

Two states are compatible if the implications are cyclic or if there are no conditions (as is the case for DE , AB etc). The compatibility IS NOT transitive

BE

BE BE CF CF BE CF

A and B

uncoditionally compatible

BE

A and C compatible if B and E compatible C and D incompatible becuase of the outputs

D,0

([AB]) ([AB], [AD]) ([AB], [AD],C, [DE]) ([AB], [AD],C, [DE], [DF]) ([AB], [AD],C, [DE], [DF], [EF]) ([AB], [AD],C])

Two by two compatible states (introducing step by step the couples)

A state can be added to a state set if compatible with all belonging states (and so on) Maximal compatibility classes ([AB], [AD],C, [DEF). NB A state can belong to more classes

SLIDE 16

16

The compatibility IS NOT transitive

A,0

00 01 11 10

B,0

,-

D,0

X1 X2

A

A,0 B,0 C,0

,-

B

,-

B,- C,1 D,-

C

A,0

,-

C,0 D,0

D A and B compatible, A and C compatible BUT B and C incompatible (output conflict) and therefore a class [ABC] is not allowed

SLIDE 17

17

NB In case of fully specified tables (without don’t cares => not possible with asynchornous systems but possible for synchronous systems) the coverture consists of all maximal classes (disjoint !) which obviously satisfy the closure condition too (indistinguishable states)

[A,B] => α [C] => β [D,E,F] => γ These are three maximal compatibility classes (not all the compatibility classes !!) which satisfy the closure and the coverture (the maximal class [AD] hasn’t been used)

A,0

00 01 11 10

B,0

,-

D,0

X1 X2

A

A,0 B,0 C,-

,-

B

,-

E,- C,1 D,-

C

A,0

,-

F,0 D,0

D

A,0 E,0 F,0

,-

E

,-

E,0 F,0

F

D,0 Compatibility classes: states set two for two compatible Maximal compatibility class: a class to which no states can be added “Coverture” condition: each state of the initial table must be present in a least one final class “Closure” condition: the future states of a class for each input , if not indifferent, must belong to the same compatibility class The set of all naximal compatibility class is always closed and and covered The minimum states set doesn’t consist necessarily of maximal classes If not all maximal classes or non-maximal classes are chosen coverture and closure must be carefully checked

SLIDE 18

A,0

00 01 11 10

B,0

,-

D,0

X1 X2

A

A,0 B,0 C,-

,-

B

,-

E,- C,1 D,-

C

A,0

,-

F,0 D,0

D

A,0 E,0 F,0

,-

E

,-

E,0 F,0

F

D,0

18

How is an asynchronous sequential network designed? - 4

4° step: coding

X1 X2

α 00 β 01 γ 11 10

NB In this coding there is a problem; races !

00 01 11 10

00,0 00,0 01,− 11,0 −,− 11,− 01,1 11,− 00,0 11,0 11,0 11,0 −,− −,− −,− −,− y2 y1 If in a table there are no multiple transitions which solve the races, the only possible solution is to increase the number of states (which allow multiple transitions removing the races) y1

00 01 11 10

X1 X2 00,0 00,0 01,− 10,0

00

−,− 11,− 01,1 11,−

01

10,0 11,0 11,0 11,0

11

00,0− −,− −,− 11,0−

10

y2

00 01 11 10

X1 X2

α,0 α,0 β,− γ,0

α

−,− γ,− β,1 γ,−

β

α,0 γ,0 γ,0 γ,0

γ [A,B] => α (right sequence) [C] => β (safe opened) [D,E,F] => γ (out of the right sequence)

SLIDE 19

19

How is an asynchronous sequential network designed ?- 5

00 01 11 10

X1 X2 00,0 01,− 10,0

00

−,− 11,− 01,1 11,−

01

10,0 11,0 11,0 11,0

11

00,0 −,− −,− 11,0−

10 Direct feedback

y1 y2

Y1= !X1y2 + y1y2 + X1!X2 Y2= X2y2 + X1X2 + X1y1 + X1y2 And with SR feedback??? Why these networks differ from the previous ones ? 1) Mealy 2) States minimization 3) Different coding Z = !y1y2 00 01 11 10

X1 X2 00,0 00,0 01,− 10,0

00

−,− 11,− 01,1 11,−

01

10,0 11,0 11,0 11,0

11

00,0 −,− −,− 11,0

10

y1 y2 00,0

SLIDE 20

20

SLIDE 21

21

Using all maximal compatibility classes - 6

[A,B] => α [C] => β [D,E,F] => γ [AD] => δ All maximal classes

What about A and D found in two maximal compatibility classes? What choice? It is indifferent, possibly avoiding the races !!!

([AB], [AD],C, [DE], [DF], [EF])

Couples of compatible states

00 01 11 10

X1 X2

α/δ,0 α,0 β,− γ/δ,0

α

−,− γ,− β,1 γ/δ,−

β

α/δ,0 γ,0 γ,0 γ/δ,0

γ

α/δ,0 α,0 γ,0 γ/δ,0

δ 00 01 11 10

X1 X2

δ,0 α,0 β,− γ,0

α

−,− γ,− β,1 γ,−

β

δ,0 γ,0 γ,0 γ,0

γ

δ,0 α,0 γ,0 γ,0

δ 00 01 11 10

X1 X2

α 00 β 01 γ 11

10,0 00,0 01,− 11,0 −,− 11,− 01,1 11,− 10,0 11,0 11,0 11,0 10,0 00,0 11,0 11,0

δ 10

A,0

00 01 11 10

B,0

,-

D,0

X1 X2

A

A,0 B,0 C,-

,-

B

,-

E,- C,1 D,-

C

A,0

,-

F,0 D,0

D

A,0 E,0 F,0

,-

E

,-

E,0 F,0

F

D,0

Multiple choices

SLIDE 22

22

00 01 11 10

X1 X2

α 00 β 01 γ 11

10,0 00,0 01,− 11,0 −,− 11,− 01,1 11,− 10,0 11,0 11,0 11,0 10,0 00,0 11,0 11,0

δ 10

This table has one column with only one stable state (input 10) and therefore no critical races. It is however always better to avoid the double state variables change. Therefore in α with input 10 we insert 01 as future state.

01,0

y1 y2

Using all maximal compatibility classes - 7 With SR ??

11,0

If we want to avoid output glitches during the transition we can insert a 0 Y2 = X1 + X2y2 Y1 = !X1!X2 + !X1y2 + X1y1 + !X2y2 Z = !y1y2 Y1= !X1y2 + y1y2 + X1!X2 Y2= X2y2 + X1X2 + X1y1 + X1y2 Z = !y1y2 Without maximal classes

SLIDE 23

23

Multiple transitions (races in green) This is a Karnaugh map

00 01 11 10 Y3Y2Y1 X2 X1 100 010 A 000 001 000 000 B 001 000 010 C 010 011 111 011 111 D 011 1 000 001 001 010 010 110

E 100
F 101

111 100 H 110 011 110

110

G 111

000

000

100

Right ? 11 00 01 11 10 10 A 00 01 00 00 B 01 00 10 C 10 11 00 11 00 D 11 1

Y2Y1

00 01 01 10 10

X2 X1

Z

00 01 11 10 Y3Y2Y1 X2 X1 011 010 A 000 001 000 000 B 001 000 010 C 010 011 000 011 000 D 011 1 000 001 001 010 010 ? ? E 100 ? ? ? F 101 ? ? H 110 ? ? ? ? G 111 ? ? ? ? ? ? ? ? ?

Z

100 110 111 011 111 110 100 000 111 110 100 000

i.e. in column 00 two stable states

SLIDE 24

24

A previous exercise again

G F E D C B A H G F E D C B

BD BD

CF

CF

CF

CF

GE

GE

00 01 11 10 X1 X2 A

A

H

C

B A

D
E

C D C 1 E B B C D A F E

G

F F H E H H G F

G

1 1 1 E

B
B

α AE β BH γ CD δ FG

00 01 11 10 X1 X2 δ α α γ β β δ α α γ γ 1 1 β α α β β γ δ δ β An asynchronous sequential network has two inputs X1 and X2 and an output Z. The inputs X1 and X2 never change at the same time. The output Z modifies its value only when a rising edge of X1

r of X2 occurs: in the first case Z=1, in the latter

Z=0

SLIDE 25

11 01

25

10,00 00,01 X1,X2 11,10 11

γ,0

10 01,11 00,01

α,0

10,00

β,1 δ,1

00 01 11 10 X1 X2 δ α α γ β β δ α α γ γ 1 1 β α α β β γ δ δ β

Resulting network

Two stable states per column; races risks !!! Please notice that the table is not primitive: this because we reach α through different paths

SLIDE 26

26

00 01 11 10 X1 X2 δ α α γ β β δ α α γ γ 1 1 β α α β β γ δ δ β

First coding (with races)

00 01 11 10 X1 X2 10 α 00 00 01 γ 01 δ 10 01 β 11 1 1 11 00 00 01 00 11 10 10 00 00 01 01 11 00 11 11 y1y2 Z = y1 Y2 = X1y2 + X1!X2 + !X2y1 Y1 = !X2y1 + X1!y2 + y1!y2

Critical race (green)

SLIDE 27

27

00 01 11 10 X1 X2 δ α α γ β β δ α α γ γ 1 1 β α α β β γ δ δ β 00 01 11 10 X1 X2 10 α 00 00 01 γ 01 δ 10 01 β 11 1 1 11 00 00 01 00 11 10 10 00 00 01 01 11 00 11 11 y1y2

Error !! 10 stable !!

Races elimination

00 01 11 10 X1 X2 10 α 00 00 01 γ 01 δ 10 01 β 11 11 00 00 01 00 11 10 10 00 00 01 01 11 00 11 11 y1y2 01

Z = y1

10

Y1 = y1y2 + !X2y1 + X1y2 + X1!X2 Y2 = !X2y1 + y1!y2 + X1!y2

SLIDE 28

28

00 01 11 10 X1 X2

010

α 000

000 011

β 001

001

δ 010

000 001

γ 011 1

001 000 −−

ε 100

−− −−

ζ 101 θ 110 η 111

−−

000 000 001 001 011 011 010 010 −− −− −− −− −− −− −− −− 111 101 100 000

?? Another solution First redundant coding

00 01 11 10 X1 X2 δ α α γ β β δ α α γ γ 1 1 β α α β β γ δ δ β

−−

SLIDE 29

X1 X2 00 01 11 10 010 α 000 000 100 β 001 001 δ 010 011 1

1

001 001 −− −− −− 000 000 001 001 000 −−

000

−− −− −− γ 100 101 110 111 010 010 100 100 −− −− −− −− −− −− −− −− −− −− −− y3 y2 y1

29

00 01 11 10 X1 X2 δ α α γ β β δ α α γ γ 1 1 β α α β β γ δ δ β

Second redundant coding γ 100 α 000 β 001 δ 010 101 011 Adjacency diagram

001 100 001

001 011 100 101 001 011

SLIDE 30

30

X1 X2 00 01 11 10 010 α 00 000 100 β 01 001 δ 10 11 1

1

001 001 −− −− −− 000 000 001 001 −− 010 010

001 100 001

001 011 101 001 011 y2 y1

y3 = 0

000

000

−− −− −− γ 00 01 10 11 100 100 −− −− −− −− −− −− −− −− −− −− −− 100

y3 = 1

y3 00 01 11 10 − − 100 1 1 1 −

100

− y2y1

Z = y1 + y2 Y3 = X1X2y1 + X1y3 Y1 = X1!X2!y3 + X1y1!y3 + !X2y1 + !X2y2 Y2 = y2!y1 + X1X2!y1!y3

Second redundant coding

SLIDE 31

31

SLIDE 32

32

A Moore asynchronous sequential network has two inputs X («Input») and CK («Clock») and an output Z («Output»). Both X and CK are initially 0. a) Upon the first positive edge of CK (0 to 1) following the condition X=1 the output becomes 1 and so remains until the successive positive transition of CK (one period is elapsed) when the output becomes in any case 0 b) The output remans 0 until after a positive edge sampling X=0. After this event back to point a) NB: In the following solution the time distance beween two consecutive positive edges of CK is called «period»

Exercise

SLIDE 33

01 01 00 10 10 10 11 00 10 00 11 10 11 01 01 11 10 00 11 00 10 01 11 11 01

C,0

00 00 X,CK

J,1

N,0

NB. After generating a 1 between two consecutive positive edges of CK, a period with output=0 is must elapse and

CK MUST sample a X=0 input before the output can become 1 again

A,0

W,1

X,0

01

B,0

10 11

Y,1 Z,1

M,0 10

Ready for activating the

utput=1

Here the output is 1 for one CK period Careful! Before a new output=1 is possible

ne period with output=0 must be elapsed

and X=0 must be sampled !

X=0 sampled Restart

M,N,R,Q -> X=1 sampled again. A period with X=0 sampled must in any case elapse

00 01 00

33

Q,0

A Moore asynchronous sequential network has two inputs X («Input») and CK («Clock») and an output Z («Output»). Both X and CK are initially 0. a) Upon the first positive edge of CK (0 to 1) following the condition X=1 the output becomes 1 and so keeps until the successive positive transition of CK when the output becomes in any case 0 b) The output keeps 0 until after a positive edge sampling X=0. After this event back to point a) Here output=0 since a period with output=1 period is elapsed

11

B

R,0

In B one period with Z=0 elapses

SLIDE 34

00 01 11 10 X, CK A B X C Y Z 1 1 J W 1 1 M N Q R W Z Y X C B A J W Z Y X C B

M

N R Q R N M J

BQ

XN AR XN XN BQ AR

CY

BQ CM AR CM AR AR CM CY BQ XN XN CM XN BQ CM YM XN AR YM AR XN AR YM

YM

ZB YM ZB

BQ
---- BQ
A

C A

B

X B X Y X

J

Y Z Y W

B

C J B J W M

W
Q

R

N

Q R B R

N

M N M M

Z
A

34

SLIDE 35

W Z Y X C B A J W Z Y X C B

M

N R Q R N M J

BQ

XN AR XN XN BQ AR

CY

BQ CM AR CM AR AR CM CY BQ XN XN CM XN BQ CM YM XN AR YM AR XN AR YM

YM

ZB YM ZB

BQ
---- BQ

00 01 11 10 X, CK A B X C Y Z 1 1 J W 1 1 M N Q R

A

C A

B

X B X Y X

J

Y Z Y W

B

C J B J W M

W
Q

R

N

Q R B R

N

M N M M

Z
A

[ABC] [AX] [YZ] [JW] [MNQ] [NR] [α] [β] [γ] [δ] [ε] [ζ]

Maximal compatibility classes

35

SLIDE 36

00 01 11 10 X, CK α,β α α,β γ β α δ δ γ δ γ 1 1 β β ε δ ε ε ε,ζ ζ ε α α α γ δ ζ ε ε,ζ ζ α 00 01 11 10 X, CK A B X C Y Z 1 1 J W 1 1 M N Q R

A

C A

B

X B X Y X

J

Y Z Y W

B

C J B J W M

W
Q

R

N

Q R B R

N

M N M M

Z
A

36

[ABC] [AX] [YZ] [JW] [MNQ] [NR] [α] [β] [γ] [δ] [ε] [ζ]

With all maximal classes

SLIDE 37

Race

37

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010

110

110 110

111

110 000 000 000 011 010 111 110 110 111 000

α β δ γ ε ζ

ABC X YZ JW MNQ NR

[ABC] [AX] [YZ] [JW] [MNQ] [NR] [α] [β] [γ] [δ] [ε] [ζ] 00 01 11 10 X, CK α,β α α,β γ β α δ δ γ δ γ 1 1 β β ε δ ε ε ε,ζ ζ ε α α α γ δ ζ ε ε,ζ ζ α

In red the chosen states

SLIDE 38

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010

110

110 110

111

110 000 000 000 011 010 111 110 110 111 101

101

− −

100

− − 100 − − 000

Multiple transition

Y2Y1Y0

38

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010

110

110 110

111

110 000 000 011 010 111 110 110 111 000

α β δ γ ε ζ Y2Y1Y0

000

SLIDE 39

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 000 011 010

110

110 111 110 110 110 110

111

111 101

101

− − 100 − − −

100

− 000

Y2Y1Y0

39

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010

110

110 110

111

110 000 000 000 011 010 111 110 110 111 101

101

− −

100

− − 100 − − 000

Y2Y1Y0

Y2,Z

Z = !Y2 Y1 Y2 = y2y1 + y2y0 + XCKy1!y0

SLIDE 40

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010

110

110 110

111

110 000 000 000 011 010 111 110 110 111 101

101

− −

100

− − 100 − − 000

Y2Y1Y0

40

Y1

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 000 011 010

110

110 111 110 110 110 110

111

111 101

101

− − 100 − − −

100

− 000

Y2Y1Y0

Y1 = Xy1 + !y2y1y0 + y2y1!y0 + !CKy1 + XCK!y2y0

SLIDE 41

41

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010

110

110 110

111

110 000 000 011 010 111 110 110 111 101

101

− −

100

− − 100 − − 000

Y2Y1Y0

000

Y0

Y2Y1Y0 00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 000 011 010

110

110 111 110 110 110 110

111

111 101

101

− − 100 − − −

100

− 000

Y0 = X!y1y0 + !X!CKy2 + X!CK!y1 + CK!y2y1y0 + !Xy2y1y0

SLIDE 42

42

SLIDE 43

43

00 01 11 10 X, CK A B X C Y Z 1 1 J W 1 1 M N Q R

A

C A

B

X B X Y X

J

Y Z Y W

B

C J B J W M

W
Q

R

N

Q R B R

N

M N M M

Z
A

Covered and closed set

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010

110

−−− 111

111

110 000 000 −−− 011 010 111 110 110 111 101

101

− −

100

− − 100 − − 000

α β δ γ ε ζ 00 01 11 10 X, CK α α α γ β α δ δ γ δ γ 1 1 β β ε δ ε ε ζ ζ ε α α −− γ δ ζ ε ζ ζ α

Non maximal classes

[ABC] [X] [YZ] [JW] [MNQ] [R] [α] [β] [γ] [δ] [ε] [ζ] [ABC] [AX] [YZ] [JW] [MNQ] [NR] [α] [β] [γ] [δ] [ε] [ζ]

Maximal classes

SLIDE 44

44

Y2,Z

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 000 011 010

110

110 111 110 110 110 110

111

111 101

101

− − 100 − − −

100

− 000

Y2Y1Y0

Z = !Y2 Y1 Y2 = y2y1 + y2y0 + XCKy1!y0

Max

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 −−− 011 010

110

110 111 110 110 −−− 111

111

111 101

101

− − 100 − − −

100

− 000

Y2Y1Y0

Z = !Y2 Y1 Y2 = y2y1 + y2y0 + XCKy1!y0

Non Max

SLIDE 45

45

Y1

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 000 011 010

110

110 111 110 110 110 110

111

111 101

101

− − 100 − − −

100

− 000

Y2Y1Y0

Y1 = Xy1 + !y2y1y0 + y2y1!y0 + !CKy1 + XCK!y2y0

Max

00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 −−− 011 010

110

110 111 110 110 −−− 111

111

111 101

101

− − 100 − − −

100

− 000

Y2Y1Y0

Y1 = Xy1 + CK!y2y0 + y2y1!y0 + !CKy1

Non Max

SLIDE 46

46

Max

Y0 = X!y1y0 + !X!CKy2 + X!CK!y1 + CK!y2y1y0 + !Xy2y1y0

Y2Y1Y0 00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 000 011 010

110

110 111 110 110 110 110

111

111 101

101

− − 100 − − −

100

− 000

Y0

Y0 = CK!y2y0 + !X!CKy2 + X!CK!y1 + y2y1y0

Y2Y1Y0 00 01 11 10 X, CK

000

000 011

001

000

010

010 011 010

011 1 1

001 001 110 010 000 000 −−− 011 010

110

110 111 110 110 −−− 111

111

111 101

101

− − 100 − − −

100

− 000

Non Max

SLIDE 47

47

SLIDE 48

50

A music playback device has volume regulation system with three keys ‘+’ , ‘–‘ and ‘■’ whose behaviour is the following; when no key is depressed – ■ + are all 0, and at any time only one key can be

depressed. A release of a key and the concurrent depression of another is impossible.
■ +

Design an asynchronous sequential circuit with two outputs I(ncrease) and D(ecrease), used to increase (ID=10) or decrease (ID=01) the volume.

If the volume must not be regulated or the as soon as ‘■’ key is depressed the volume must not

change.

When the +’ ( ‘–‘) key is depressed the volume must be increased (decreased) upon the release of

the key. The increase (decrease) of the volume stops either when the +’ ( ‘–‘) is released after being depressed again or as soon as ‘■’ is depressed.

If ‘–‘ (+) is depressed while the volume increases (decreases) the volume change is stopped

immediately and is reversed as soon as ‘–‘ (+) key is released

SLIDE 49

000,-0 001,10 + key depressed

again - Ready to stop volume change

000,-0 + key released

Volume increase

51

010,00 000,00

D

001,10 001,00 + key depressed

Surely a simmetrical state diagram!

Here the output is a «don’t care» because it does not matter when the output changes

If the volume must not be regulated or as soon as when the ‘■’ key is depressed the volume must not change

000,0- 000,0-

key released

Volume decrease

100,01

key depressed

again - Ready to stop volume change

100,01 001,0-

Volume decrease immediate stop

000,01

G

010,0-

■ Key depressed Volume decrease Immediate stop

010,00

E

010,-0

■ Key depressed Volume increase Immediate stop

100,-0

Volume decrease immediate stop

000,10

C

100,00

F

001,00

B

100,00

key depressed

000,00

A

■+,ID

H

When the +’ ( ‘–‘) key is depressed the volume must be increased (decreased) upon the release of the key. The volume increase (decrease)

stops either when the +’ ( ‘–‘) is released after being depressed again or as soon as ‘■’ is depressed.

If ‘–‘ (+) is depressed while the volume increases (decreases) the volume change must sbe reversed as soon as ‘–‘ (+) key is released

Vivado Volume_regulator

SLIDE 50

52

AG

G F

E
D

C

AC

B A H G

AG

F

E

D C

AC

B

AG AG CG

AC

AC

Maximal compatibility classes [AE],[B],[C],[DEH],[F],[G] For the coverture all of them are necessary But could I leave A alone ? X1 = - X2 = ■

A B C D E F

X3 = +

G

A,00

000 001 011 010

B,00 -,- E,00 C,-0 B,00 -,-

,-

C,10 D,10 -,- E,-0 A,-0 D,10 -,-

,-

A,00 -,-

,-

E,00 G,0- -,-

,-

G,01 B,0- -,- E,0- A,0- -,-

,-

H

F,00

100 101 111 110

,-
,-
,-
,-
,-
,-
,-

F,-0

,-
,-
,-
,-
,-
,-
,-
,-
,-
,-
,-

F,00 -,-

,-

H,01 -,-

,-
,-

H,01 -,-

,-
,-
,-
,-
,-

Yes, because the only group of states remains (DEH) whose future states for the same input belong to the same group of states (A,D,H)

SLIDE 51

53

[AE] => α [B] => β [C] => χ [DEH] => δ [F] => φ [G] => γ

X1 = - X2 = ■

A B C D E F

X3 = +

G

A,00

000 001 011 010

B,00 -,- E,00 C,-0 B,00 -,-

,-

C,10 D,10 -,- E,-0 A,-0 D,10 -,-

,-

A,00 -,-

,-

E,00 G,0- -,-

,-

G,01 B,0- -,- E,0- A,0- -,-

,-

H

F,00

100 101 111 110

,-
,-
,-
,-
,-
,-
,-

F,-0

,-
,-
,-
,-
,-
,-
,-
,-
,-
,-
,-

F,00 -,-

,-

H,01 -,-

,-
,-

H,01 -,-

,-
,-
,-
,-
,-

X1 = - X2 = ■ X3 = +

α,00

000 001 011 010

β,00 -,- α/δ,00 χ,-0 β,00 -,-

,-

χ,10 δ,10 -,- α/δ,-0 α,00 δ,10 -,- α/δ,00 γ,0-

,-
,-

γ,01 β,0-

,-

φ,00

100 101 111 110

,-
,-
,-
,-
,-
,-
,-

φ,-0

,-
,-
,-

δ,01 -,-

,-
,-

φ,00 -,-

,-
,-

δ,01 -,-

,-
,-

[AE] => α [B] => β [C] => χ [DEH] => δ [F] => φ [G] => γ

,-

α/δ,0-

But we use in this case the maximal classes

If we had used non maximal classes the only difference would have been δ (E) where we have now α/δ

SLIDE 52

54 X1 = - X2 = ■ X3 = +

α,00

000 001 011 010

β,00 -,- α,00 χ,-0 β,00 -,-

,-

χ,10 δ,10 -,- α,-0 α,00 δ,10 -,- α,00 γ,0-

,-
,-

γ,01 β,0-

,-

φ,00

100 101 111 110

,-
,-
,-
,-
,-
,-
,-

φ,-0

,-
,-
,-

δ,01 -,-

,-
,-

φ,00 -,-

,-
,-

δ,01 -,-

,-
,-

[AE] => α [B] => β [C] => χ [DEH] => δ [F] => φ [G] => γ

,-

α,0-

,-

X1 = - X2 = ■ X3 = +

000,00

000 001 011 010

001,00 -,- 000,00 011,-0 001,00 -,- 011,10 010,10 -,- 000,00 010,10 -,- 000,00 101,0-

,-
,-
,-

101,01 001,0- -,-

,-
,-
,-
,-
,-
,-
,-

100,00

100 101 111 110

,-
,-
,-
,-
,-
,-
,-
,-
,-

010,01 -,-

,-
,-

100,00

,-
,-
,-
,-
,-
,-
,-
,-
,-
,-
,-
,-
,-

α 000 β 001 χ 011 δ 010 φ 100 γ 101

y3 y2 y1

111 110

,-

000,-0 000,0-

,-

100,-0 010,01

,-
,-

010,-0 111,-0 110,-0 100,-0

No way with this coding Find and alternative coding!!

000,0- 100,0-

SLIDE 53

55

Can we transform a Moore table into a Mealy table?

B 00 01 11 10 A A A

X1X2

A B C A A B A C D A C A A D A 1 D

Moore

B,0

00 01 11 10

A,0 A,0 A,0

X1X2

A

B,0 C,0 A,0 A,0

B

A,0 C,0 D,1 A,0

C

A,0 A,0 D,1 A,0

D

Mealy

B,0

00 01 11 10

A,0 A,0 A,0

X1X2

A

B,0 C,0 A,0 A,0

B

A,0 C,0 D,- A,0

C

A,- A,- D,1 A,-

D

Mealy

Let’s associate to each transition the

utput value of the

destination state (or

f the source state)

Obviously in the transitions the outputs can be don’t care if we are not interested whether the network anticipates or delays the outputs

SLIDE 54

56 B,1

00 01 11 10

A,0 A,1 A,1 X1X2

A

B,1 C,- A,1 A,-

B

A,1 C,0 D,1 A,0

C

A,- A,0 D,1 A,1

D

Mealy

A state stable with different

utputs. The stable states

with different outputs must be doubled (or quadrupled etc.). Here B and D stable with

utput 1 and therefore

transition to A1

Moore

Stable

utput 1

B

00 01 11 10

A0 A1 A1

X1X2

A0

B C A1 A1

B

A1 C D A0

C

A1 A0 D A1

D

B A0 A1 A1

A1

1 1 1 Can we transform a Mealy table into a Moore table?

SLIDE 55

01 00 11

57

A particular synthesis - 1

Design an asynchronous sequential network whose output Z assumes the value of the input D upon the positive transition (sampling) of an input C(lock). The output is stable until C samples a different input. (Obviously a symmetrical diagram) 01 11 11 B,0 01 00 11 01 10 10 DC 11 01 10 00 01 10 10 11 00 00 10

D

G

00 01 11 10

A B

C

A

A

B C

B

G

D

C

E

D H

D

F E D

E

F A

H

F

G A

C

G

F

D

H

H 1 1 1 1

00 C,0 D,1 H,1 E,1 F,1 A,0 G,0

A one is sampled: the

utput changes

A zero is sampled: the

utput changes

Blue states => output 0 stable Red states => output 1 stable Yellow states are the only states from where an output change can occur

SLIDE 56

58

A particular synthesis - 2

G

00 01 11 10

A B

C

A

A

B C

B

G

D

C

E

D H

D

F E D

E

F A

H

F

G A

C

G

F

D

H

H 1 1 1 1

D

α

00 01 11 10

α α β

C

α

α −− γ β

β

δ γ γ γ

γ

δ α −− γ

δ 1 1

D

00

00 01 11 10

00 00 01

C

00

00 −− 11 01

01

10 11 11 11

11

10 00 −− 11

10 1 1

D y2 y1

BD

BD

AE

AE

B

C D E F G H A B C D E F G

[ABG] => α [C] => β [DEH] => γ [F] => δ Here we don’t use the maximal compatibility classes but coverture and closure are verified

SLIDE 57

59

00

00 01 11 10

00 00 01

C

00

00 −− 11 01

01

10 11 11 11

11

10 00 −− 11

10

D y2 y1

A particular synthesis - 3

1 1

Y1= Y2C + Y1!C Y2= Y2C + D!C Z = Y1

D(elay) Flip Flop – The D name will be explained later - The arrows indicate the output variations It is the only FF used in the synchronous networks

NB: The correct behaviour takes for granted obviously (as is the case with all asynchronous networks) that the input D is stable during the transition 0 to 1 of the C(lock) (β−>γ and δ−>α) which means the a little time τ1 (setup time) before the C transition and τ2 (hold time) after the C transition D must be stable. τ1 and τ2 values depend on the technology. If this condition is violated the output behaviour is unpredictable (aliasing - metastability) α β γ δ

SLIDE 58

60

How must this circuit be modified in order to insert two inputs Reset (Z=0) and Preset (Z=1)? Notice that if both true and inverted values of the output an inverter should be added. BUT in this case the two outputs wouldn’t be synchronous

!Z

Y1=Z

SLIDE 59

D Flip-Flop

DFF

D CK Q

FFD: An asynchronous sequential network whose output Q copies the logical value of D input during the rising edges (positive edge triggered) of input CK The FFD is typically used as memory elementary cell in the synchronous sequential networks (see later). In that case CK signal normally (but not necessarilty) has a periodical waveform (clock).

61

CK D Q

No change without ck

SLIDE 60

Correct use of DFF Setup (tSU), Hold (tH) and Answer (tR) times

DFF

D CK Q

D CK Q CK D Q

τH τSU τR The behaviour is correct only if tSU≥ tSUmin and tH ≥ tHmin, otherwise metastability.

62

SLIDE 61

63

Metastability CK D

τH τSU

Q1 Q2 Q3 Unpredictable and non-repetitive behaviour

SLIDE 62

CD Latch

CD C D Q Q*

C D Q Q* C D 1 1 1 1 Q Q* Q Q* Q Q* 1 1 Q*

SR S R Q Q*

C D Q

τSU ≥ τSUmin τH≥ τHmin Constraints: Response time τR = τSU+ τH

C D Q

τSU τH

64

SLIDE 63

65

CD Latch

11 B,1 01 11 01 00 10 10 E,0 00 C,0 10 D,1 00 11 10 11 00 10 00 F,1 01 01 A,0 DC

[ACE] [BDF] α β

B C D E F A B C D E

C

00 01 11 10

A B

C

A

A

B D

B C D

C

E

E F 1 1 1

D

C A E D F A F D A

B
α

00 01 11 10

α β α

C

α

β α β β

β 1

D

00 01 11 10

1

C

1 1 1

1 1

D

y Y= CD + !Cy With SR ? How would you implement a Latch from a state table or a DFF with a two inputs MUX ?

SLIDE 64

66

DFF

D CK Q

D CK Q Mux O 1 S

CD Latch

SLIDE 65

67

373

D0 D1 D2 D3 D4 D5 D6 D7 00 O1 O2 O3 O4 O5 O6 O7 CK OE*

74XX373 CK Di Qi OE* Oi

Z

C Qi D CK Di OE* Oi

Latch CD

8 bit Latch register 3-state outputs

SLIDE 66

68

374

D0 D1 D2 D3 D4 D5 D6 D7 00 O1 O2 O3 O4 O5 O6 O7 CK OE*

74XX374 CK Di Qi OE* Oi

Z

8 bit Edge-Triggered register 3-state outputs Qi D CK Di OE* Oi

Flip-Flop D

SLIDE 67

69

SLIDE 68

70

SLIDE 69

71 71

SLIDE 70

72

D type FF 7474

As is the case with all FFs it is required that both true and inverted outputs are available at the same time. To this end in pratice the DFF is synthesized with a redundant coding using three state variables (R,S e Q) with the following schematic CP=CK

SLIDE 71

73

Edge Triggered DFF with SET and PRESET

!Asynchronous Set !Asynchronous Reset

Obviously both !S and !R must not be 0 concurrently (what happens in this case ?)

SLIDE 72

74

SLIDE 73

75

SLIDE 74

76

SLIDE 75

77

SLIDE 76

78

SLIDE 77

79

C

Analysis … three state variables S R Q If here S+R=1 Q and !Q are complementary (NB Here !S is indicated as S and !R as R) Asybchronous Set and missing

Not reachebale or instable

X

If S=0 (=> R=1) and C=1 then Q=1 and D has no impact (row 011 right columns-> S is independent from X). If C=0 (left columns) the future state is 111 (S=R=1) and Q does not change Only stable states: if S=R=0 and Q any value the state is unstable (if S=0 then R=1 ) S= 0 R=1 and Q=0 is impossible (S=0 implies Q=1) S= 1 R=0 e Q=1 is impossible (R=0 implies Q=0) If C=0 => S=R=1 and then Q stable (in green) Q switch Row 111 and 110 (S=R=1). With C=0 Q is stable. If C becomes 1 with D=1 then X=0 and then R remains 1 and only S changes which becomes 0 and therefore Q=1 and !Q==0. If D=0 then X=1 and with C=1 R becomes 0 (while S remains 1 ) and therefore !Q=1 and Q=0.

C D 00 01 11 10 −−− 000 −−− −−− 001 −−− 010 011 −−− −−− 111 011 011 −−− −−− −−− −−− 110 111 110 111 011 100 100 101 110 111 −−− −−− 100 100 110 110 011 100 −− −− −− −− −− S R Q 111 C=0 C=1

First level FFs are NOT SR (the outputs are not complementary)

NB: Here X is not equal to !R (S=0 R=1 D=0 -> X=1)

SLIDE 78

80

C D 00 01 11 10 −−− 000 −−− −−− 001 −−− 010 A 011 −−− −−− 111 011 011 −−− −−− −−− −−− 110 111 110 111 011 100 B 100 101 D 110 C 111 −−− −−− 100 100 110 110 011 100 −− −− −− −− −− −− 111 S R Q A 011 C,1 A,1 A,1 D,0 C,1 D,0 C,1 A,1 B,0 B 100 D 110 C 111 B,0 B,0 D,0 D,0 A,1 B,0

C,1

C D 00 01 11 10

“De-synthesizing” …

A 00 10,1 00,1 00,1 11,0 10,1 11,0 10,1 00,1 01,- B 01 D 11 C 10 01,0 01,0 11,0 11,0 00,- 01,0

10,1

C D 00 01 11 10 Y2Y1

Critical races!

A 00 10,1 00,1 00,1 11,0 10,1 11,0 10,1 00,1 11,- B 01 D 11 C 10 01,0 01,0 11,0 11,0 10,- 01,0

10,1

C D 00 01 11 10 Y2Y1

Multiple transitions Arrows for the Q transitions Don’t care for unreachable states

SLIDE 79

81

Y1 = !Cy1 + !y2y1 + C!Dy2

A 00 10,1 00,1 00,1 11,0 10,1 11,0 10,1 00,1 11,- B 01 D 11 C 10 01,0 01,0 11,0 11,0 10,- 01,0

10,1

C D 00 01 11 10 y2y1

Y2 = !C + !Dy2!y1 + Dy2y1 Z = !y1

Synthesis… But y2 is not the complement of y1: it is not a FF in strict sense

SLIDE 80

82

C D 00 01 11 10 −−− 000 −−− −−− 001 −−− 010 011 −−− −−− 111 011 011 −−− −−− −−− −−− 110 111 110 111 011 100 100 101 110 111 −−− −−− 100 100 110 110 011 100 −− −− −− −− −− −− 111 S R Q

Re-syntehesizing…

C

Races removal

Races

C D 00 01 11 10 −−− 000 −−− −−− 001 −−− 010 011 −−− −−− 111 011 011 −−− −−− −−− −−− 110 111 110 111 011 101 100 101 110 111 −−− 011 100 100 110 110 010 100 −− −− −− 100 −− −− 111 S R Q

Non minimal synthesis

S = !C + !DS + S!R = !C + S(!R + !D)= !C +S !(RD) =!(C !(S !(RD))) R = !C + !S + RD = !(C S !(RD)) Q = !S + RQ = !(S !(RQ))

SLIDE 81

84

7474 – Schematic 2