Development of Flip Chip Assembly Services MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble - France CMP annual users meeting, 4 Feb. 2016, PARIS
Summary ry Motivation and objectives Development of Flip Chip Assembly offer - UBM and Solder bumping - Substrates and micro assembly Offer example CMP annual users meeting, 4 Feb. 2016, PARIS
Motivation and objectives Flip chip bonding advantages • Improving the IC performances: - Reducing the parasites - Increasing the I/Os output speed & bandwidth - Improving the precision - Reducing the losses • Minimizing the assembly volume - Miniaturization - Power Density - Optimized Commutation Cells • Increasing the thermal interfaces between the IC and the ambient - Better thermal management CMP annual users meeting, 4 Feb. 2016, PARIS
Motivation and objectives Flip chip prototyping flow • Major drawbacks - Complex process flow - High engineering effort CMP Flip Chip Assembly Services - Long processing delays - Increased cost - Increased failure risk Design & fabrication Flip chip assembly Bumping UBM IC Scheduling process Case study DRC Fabrication UBM & Bumping OK? Setup cost/NRE OK? Al e-Ni/Au Scheduling process Design Setup cost/NRE STOP Substrate Assembly DRC Case study Fabrication Flip Chip OK? OK? Scheduling Scheduling process process Setup cost/NRE Setup cost/NRE STOP CMP annual users meeting, 4 Feb. 2016, PARIS
Motivation and objectives Objectives • Offer a wide range of Flip Chip Packaging options - Bumping & mounting onto different substrates • Customer support: - Add-on Flip Chip Packaging design kit (FCP Add-on on request) - Chip and substrate co-design verification • Turn around time optimization - Single procedure avoiding case by case processing IC - Prequalified subcontractor engineering effort Fabrication • Cost optimization: DRC OK? Design Substrate & Packaging - Setup and tooling cost sharing Flip Chip CMP annual users meeting, 4 Feb. 2016, PARIS
Development of FC Assembly offer UBM and Solder bumping • Single die processing is possible! - In order to reduce the setup cost and to minimize the engineering effort a fixed chip pad ring will be proposed (few options would be made available depending on the customers’ needs) - Compatible with fine pitch substrates - CMP Design verification - Custom chip size and pad locations can be processed upon request Chip pad ring CMP annual users meeting, 4 Feb. 2016, PARIS
Development of FC Assembly offer Substrates and micro assembly • Substrates: CPA - - Pre-specified land pattering compatible with the fixed pad rings (few designs are possible depending on the customers’ needs ) - Custom designs upon request - CMP Design verification - Minimized engineering effort (NRE) - Setup cost reduction - Substrate types: organic, ceramic • Micro assembly: CPA - - CMP Chip/substrate co-design verification - Minimized engineering effort (NRE) - Setup cost reduction thanks to the normalized designs of the IC & the substrate - Substrate types: organic, ceramic, silicon
Study of optimal pad ring s size & I/ I/O AMS circuits in 2015: ST circuits 28nm and 65nm in 2013 and 2014: • Around 80% of the AMS circuits have: • Around 80% of the STM circuits have : - Surface < 10mm² - Surface < 1,6mm² - I/Os < 84 - I/Os < 64 • Around 80% of the packaged AMS • All packaged STM circuits (80%) have: circuits (65%) have: - Packages with < 64 I/Os - Packages with < 84 I/Os - Square packages - Square packages CMP annual users meeting, 4 Feb. 2016, PARIS
Study of optimal pad ring s size & I/ I/O Main challenges • Cost: - Will I be charged for the total pad ring size if my IC is smaller? Yes, but CMP offer will be made so that it is cost effective even for the smallest IC sizes. However, each technology has a different cost gain. Worst case target is 20% reduction. • Size and I/O: - My design is bigger and/or has more I/Os than the pad ring. Few options would be made possible depending on the customers’ needs CMP Offer cost reduction for single die processing* as a function of the IC size for fixed pad ring: *UBM + Bumping + Flip Chip assembly of 30 naked dies processed by PacTech 85 Example A: Example B: 100%=Standard cost 100%=Standard cost 95 Pad ring 48 I/O Pad ring 100 I/O 80 90 S=8mm² S=11,8mm² CMP offer, [%] CMP offer, [%] 75 85 80 70 C18/H18 75 C18/H18 C35B4C3 65 C35B4C3 H35D4B3 70 S35D4M5 S35D4M5 60 65 3,4 4,3 5,2 6,1 7 3,4 4,8 6,2 7,6 9 IC size, [mm²] IC size, [mm²]
Thank you ! Lyubomir.Kerachev@imag.fr CMP annual users meeting, 4 Feb. 2016, PARIS
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