Assembly Services MPW Services Center for IC / MEMS Prototyping - - PowerPoint PPT Presentation

assembly services
SMART_READER_LITE
LIVE PREVIEW

Assembly Services MPW Services Center for IC / MEMS Prototyping - - PowerPoint PPT Presentation

Development of Flip Chip Assembly Services MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble - France CMP annual users meeting, 4 Feb. 2016, PARIS Summary ry Motivation and objectives Development of Flip Chip


slide-1
SLIDE 1

Development of Flip Chip Assembly Services

MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble - France

CMP annual users meeting, 4 Feb. 2016, PARIS

slide-2
SLIDE 2

Summary ry

CMP annual users meeting, 4 Feb. 2016, PARIS

Motivation and objectives Development of Flip Chip Assembly offer

  • UBM and Solder bumping
  • Substrates and micro assembly

Offer example

slide-3
SLIDE 3

Motivation and objectives

CMP annual users meeting, 4 Feb. 2016, PARIS

Flip chip bonding advantages

  • Improving the IC performances:
  • Reducing the parasites
  • Increasing the I/Os output speed & bandwidth
  • Improving the precision
  • Reducing the losses
  • Minimizing the assembly volume
  • Miniaturization
  • Power Density
  • Optimized Commutation Cells
  • Increasing the thermal interfaces between the IC and the ambient
  • Better thermal management
slide-4
SLIDE 4

Flip chip prototyping flow

  • Major drawbacks
  • Complex process flow
  • High engineering effort
  • Long processing delays
  • Increased cost
  • Increased failure risk

Motivation and objectives

CMP Flip Chip Assembly Services

Flip chip assembly

Design Substrate IC DRC OK? DRC OK? Fabrication Fabrication

Case study UBM & Bumping OK?

UBM Bumping Assembly

Setup cost/NRE Scheduling process

Case study Flip Chip OK?

Design & fabrication

CMP annual users meeting, 4 Feb. 2016, PARIS

STOP STOP

Setup cost/NRE Scheduling process Setup cost/NRE Scheduling process Setup cost/NRE Scheduling process Al e-Ni/Au

slide-5
SLIDE 5

CMP annual users meeting, 4 Feb. 2016, PARIS

Objectives

  • Offer a wide range of Flip Chip Packaging options
  • Bumping & mounting onto different substrates
  • Customer support:
  • Add-on Flip Chip Packaging design kit (FCP Add-on on request)
  • Chip and substrate co-design verification
  • Turn around time optimization
  • Single procedure avoiding case by case processing
  • Prequalified subcontractor engineering effort
  • Cost optimization:
  • Setup and tooling cost sharing

Design Flip Chip IC DRC OK? Substrate Fabrication & Packaging

Motivation and objectives

slide-6
SLIDE 6

CMP annual users meeting, 4 Feb. 2016, PARIS

Development of FC Assembly offer

  • Single die processing is possible!
  • In order to reduce the setup cost and to minimize the engineering effort a

fixed chip pad ring will be proposed (few options would be made available depending on the customers’ needs)

  • Compatible with fine pitch substrates
  • CMP Design verification
  • Custom chip size and pad locations can be processed upon request

UBM and Solder bumping

Chip pad ring

slide-7
SLIDE 7

Development of FC Assembly offer

Substrates and micro assembly

  • Substrates:
  • Pre-specified land pattering compatible with the fixed pad rings

(few designs are possible depending on the customers’ needs)

  • Custom designs upon request
  • CMP Design verification
  • Minimized engineering effort (NRE)
  • Setup cost reduction
  • Substrate types: organic, ceramic
  • Micro assembly:
  • CMP Chip/substrate co-design verification
  • Minimized engineering effort (NRE)
  • Setup cost reduction thanks to the normalized designs of the IC & the substrate
  • Substrate types: organic, ceramic, silicon

CPA - CPA -

slide-8
SLIDE 8

Study of optimal pad ring s size & I/ I/O

CMP annual users meeting, 4 Feb. 2016, PARIS

AMS circuits in 2015:

  • Around 80% of the AMS circuits have:
  • Surface < 10mm²
  • I/Os < 84
  • Around 80% of the packaged AMS

circuits (65%) have:

  • Packages with < 84 I/Os
  • Square packages

ST circuits 28nm and 65nm in 2013 and 2014:

  • Around 80% of the STM circuits have:
  • Surface < 1,6mm²
  • I/Os < 64
  • All packaged STM circuits (80%) have:
  • Packages with < 64 I/Os
  • Square packages
slide-9
SLIDE 9

Study of optimal pad ring s size & I/ I/O

  • Cost:
  • Will I be charged for the total pad ring size if my IC is smaller?

Yes, but CMP offer will be made so that it is cost effective even for the smallest IC sizes. However, each technology has a different cost gain. Worst case target is 20% reduction.

  • Size and I/O:
  • My design is bigger and/or has more I/Os than the pad ring.

Few options would be made possible depending on the customers’ needs

CMP Offer cost reduction for single die processing* as a function of the IC size for fixed pad ring:

*UBM + Bumping + Flip Chip assembly of 30 naked dies processed by PacTech

Main challenges

Example A:

Pad ring 48 I/O S=8mm²

Example B:

Pad ring 100 I/O S=11,8mm² 65 70 75 80 85 90 95 3,4 4,8 6,2 7,6 9

CMP offer, [%] IC size, [mm²]

C18/H18 C35B4C3 H35D4B3 S35D4M5

60 65 70 75 80 85 3,4 4,3 5,2 6,1 7

CMP offer, [%] IC size, [mm²]

C18/H18 C35B4C3 S35D4M5

100%=Standard cost 100%=Standard cost

slide-10
SLIDE 10

Thank you !

Lyubomir.Kerachev@imag.fr

CMP annual users meeting, 4 Feb. 2016, PARIS