ASIC QA/QC for DUNE Carl Bromberg, Kendall Mahn, Dean Shooltz, - - PowerPoint PPT Presentation

ASIC QA/QC for DUNE

Carl Bromberg, Kendall Mahn, Dean Shooltz, Daniel Douglas Michigan State University July 16-18, 2018

• C. Bromberg - CE Workshop 2018

Cold ASIC QA/QC before FEMB produc:on?

• CE is tricky w/many constraints: e.g., seamless operaLon warm & cold
• Foundry or Packaging issues can occur at any Lme.
• Single channel failure rate goal is low, and failed chip rate goal is zero.
• Reworked FEMB are likely to have reliability problems
• Hot air removal and soldering of chips will affect their long-term reliability
• Other components (R & C, Diodes & Reg.) may be weakened with long-term

reliability issues

• Discarding many below par FEMB could cost $M’s
• If ASIC cold tests are safe, feasible & cost effec(ve, why not do it?
• C. Bromberg - CE Workshop 2018

What channel/chip failure rate is acceptable?

• 0.1% channel failure is a few dead wires per APA
• Without cold QA, ProtoDUNE FE failures would have been 40 Lmes 0.1
• With cold QA, ProtoDUNE FE ASIC beat the 0.1% dead channel rate.
• Our desires are closer to a few dead channels/detector, < 0.001% rate
• Note: FEMB readout mixes x, u, v: full ASIC failures are really bad.
• A 2D reconstrucLon dead-spot (~ 4x4 cm2) generated if FE or ADC failure
• A 2D reconstrucLon dead-spot (~ 8x8 cm2) generated if ColdDATA failure
• For FE and ADC, QA/QC tests must select 24,000 chips in ~ 6 months
• C. Bromberg - CE Workshop 2018

Feasibility of Cold ASIC QA/QC

• Dean and I learned a few things during the MSU CTS development
• EliminaLng H2O from cold tesLng was essenLal for reliable CE R&D & QA/QC
• Have to take safety reviews seriously- it takes real Lme and effort to go from

prototype to approved device

• ASIC test clamp works if H2O avoided.
• Quad Clamp Boards did QA/QC for the FE ASIC and likely can do ADC (ColdDATA?)
• CTS & Quad Board does 4 ASIC QA/QC in < 60 minutes (15 min/ASIC)
• To avoid mechanical damage, use automated loading of chips into Quad Boards
• To use OCR, put serial numbers on the ASIC chips when packaged
• To get 24,000 good ASICs selected in < 6 months (2 min/ASIC)
• More ASICs done in parallel - perhaps factor of 4
• Cycle Lme reducLons – perhaps a factor of 2
• C. Bromberg - CE Workshop 2018

RTS Conceptual Design

• RoboLc loading & unloading of Quad Clamp Boards
• Buy Commercial SCARA robot (Epson T3 or similar for about $10k)
• Robot can open/close test clamps, or operator does
• Include vision based system with OCR (opLcal character recogniLon)
• Robot Tasks
• Vision based inspecLon of chips (bent leads?)
• OCR (opLcal character recogniLon) for ASIC ID (serialized at fab house)
• Load chips into Quad Clamp test boards
• Unload chips from test boards into pass/fail trays
• Tray-to-tray chip sorLng (if we get into cherry-picking ASICs)
• C. Bromberg - CE Workshop 2018

RTS Conceptual Design

• RoboLc loading of Quad Clamp Boards
• Buy Commercial Pick & Place Machine
• Quad Clamp Boards loaded/unloaded by Pick & Place Machine
• A Framework hand loaded & cabled with many verLcal Quad Clamp Boards
• Two styles possible for Quad FE ASIC Board (similar design for ADC, ColdDATA)

Quad FE ASIC Board 64 single-ch. ADCs FPGA Mezz

ASIC ASIC ASIC ASIC

LN2 Level Quad FE ASIC Board 64 single-ch. ADCs FPGA Mezz

ASIC ASIC ASIC ASIC

LN2 Level Flexible Cables

• C. Bromberg - CE Workshop 2018

RTS Conceptual Design

• N2 Enclosure
• CTS-like LN2 chamber at floor level with “Gate Valve” Lid
• Door to N2 enclosure
• C. Bromberg - CE Workshop 2018

LN2 Test Chamber N2 Enclosure * * * Frame w/mulLple Quad Boards Gate Valve Door Open LN2 Level

RTS Conceptual Design

• Frame posiLoned in N2 enclosure, cables connected, Door closed
• N2 Enclosure Purged with N2 Gas at high flow rate
• C. Bromberg - CE Workshop 2018

LN2 Test Chamber N2 Enclosure * * * Gate Valve Door closed LN2 Level

RTS Conceptual Design

• Gate Valve opened
• Frame lowered into LN2 Test chamber to Cool Level
• Strong Fans circulate N2 gas to cool ASIC loaded Quad Clamp Boards
• C. Bromberg - CE Workshop 2018

LN2 Test Chamber N2 Enclosure Gate Valve Door closed * * * LN2 Level

RTS Conceptual Design

• Frame lower ASIC Clamps into LN2
• ASIC tests on each Quad Clamp Board run in parallel
• C. Bromberg - CE Workshop 2018

LN2 Test Chamber N2 Enclosure Gate Valve Door closed * * * LN2 Level

RTS Conceptual Design

• Frame raised into N2 Enclosure
• Gate Valve closed
• Hot N2 gas circulated to bring Quad Boards rapidly to Room Temp.
• C. Bromberg - CE Workshop 2018

LN2 Test Chamber N2 Enclosure Gate Valve Door closed * * * LN2 Level

RTS Conceptual Design

• Frame removed from N2 enclosure and Cables removed
• Quad Boards have ASICs removed by Pick & Place machine
• New Frame loaded and cycle starts again.
• C. Bromberg - CE Workshop 2018

LN2 Test Chamber N2 Enclosure Gate Valve Door Open * * * LN2 Level

More Elaborate RTS Conceptual Design

• N2 Enclosure
• Input and Output N2-Locks
• Open top CTS-like LN2 chamber at floor level
• Cabling sealed below floor and moves with Framework
• C. Bromberg - CE Workshop 2018

Open Top LN2 Test Chamber N2 Enclosure Output N2-Lock Purge & Warm * * * Frame w/mulLple Quad Boards Input N2-Lock Purge

RTS Throughput & Cost

• Loading and Unloading Quad Boards done in parallel with tesLng
• TesLng done on each Quad Board in parallel
• Full cycle of say 16 ASIC chips takes 1/2 hour ( 2 minutes/ASIC)
• C. Bromberg - CE Workshop 2018
• Conserva(ve esLmate based on Design/Prototype Time: 1.5 years
• One (DS) Full-Lme Engineer-Fabricator-Programmer ($400k)
• M&S for prototype ($75k), 3 producLon units ($150k)
• ProducLon Units Assembly & TesLng ($100k)
• OperaLon of 3 RTS units, 6 students for 6 months ($100k)
• Total = $750k --- Compare to cost of discarding 500 FEMB ($2.5M ?)
• MSU can produce RTS. We want to parLcipate in ASIC & FEMB QA/QC

Costs (fully loaded)